LC_CTRL Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.480s	136.913us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	23.210us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	16.987us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.090s	613.674us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	69.828us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.900s	54.118us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	16.987us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	69.828us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.690s	115.294us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.730s	378.019us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	14.124us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.990s	524.321us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.620s	9.045ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_prog_failure	3.990s	524.321us	50	50	100.00
		lc_ctrl_errors	20.620s	9.045ms	50	50	100.00
		lc_ctrl_security_escalation	15.760s	486.282us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.352m	3.496ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.900s	705.741us	20	20	100.00
		lc_ctrl_jtag_errors	1.280m	11.749ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	7.690s	645.018us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.480s	3.853ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.900s	705.741us	20	20	100.00
		lc_ctrl_jtag_errors	1.280m	11.749ms	19	20	95.00
		lc_ctrl_jtag_access	25.620s	1.157ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.000s	2.367ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.670s	2.259ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.610s	326.409us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	58.570s	2.687ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.480s	573.803us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.680s	94.330us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.250s	324.814us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.850s	57.423us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.610s	3.315ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.260s	15.360us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.678m	24.056ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.470s	115.858us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.000s	148.417us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.000s	148.417us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	23.210us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	16.987us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	69.828us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	36.280us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	23.210us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	16.987us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	69.828us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	36.280us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
		lc_ctrl_tl_intg_err	5.730s	280.971us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.730s	280.971us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.730s	378.019us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.870s	386.559us	50	50	100.00
		lc_ctrl_sec_cm	41.240s	409.973us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.760s	486.282us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.690s	115.294us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.480s	3.853ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.760s	2.054ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.760s	2.054ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.560s	625.276us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.550s	651.540us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.550s	651.540us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	41.249m	77.272ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	97.29	95.43	91.98	97.67	96.13	98.48	94.64

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 28 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 28 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.12029014048101700917723430033918338476786700253953884609709941975017275526924
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1dc12c5b-669c-4204-a8c0-bc6ad2edafb2
```
  - 4.lc_ctrl_stress_all_with_rand_reset.4497743272020384298767050988955475390938061367157036599148752963604984153891
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8a004a7a-2eb7-4142-a449-8880c43bb5c2
```
  - ... and 26 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 9 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.77274560982088178605293089374913651771307161760090266202417885335694945072241
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:59ccef99-0068-4222-a23b-f0dc48b95c5f
```
  - 5.lc_ctrl_stress_all_with_rand_reset.28556707334943047855181386813401940589814402712069375602826472032314996237244
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:720f8ae8-6b55-4034-8316-390d7607a637
```
  - ... and 7 more failures.
UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.114332470071445140440878690262651008589838738238361916339729374274031334721409
    Line 34623, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28339594857 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x1ed87600
  UVM_INFO @ 28339594857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.lc_ctrl_stress_all_with_rand_reset.32913992104997467099683703240664476115618298443605731154648758903253466273428
    Line 10319, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19637040894 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x4734c000
  UVM_INFO @ 19637040894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 16.lc_ctrl_stress_all_with_rand_reset.44911002609354392271945180924449346396834478815941367051219046805867542696798
    Line 59644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66873220696 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
  UVM_INFO @ 66873220696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.lc_ctrl_stress_all_with_rand_reset.79500590102926970115940986537424001761388129260731263915933409110342936707675
    Line 8564, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5705371108 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
  UVM_INFO @ 5705371108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.68211011697078968261111735538271074572943561495574721205444977686985602921181
    Line 14248, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5563504541 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 5563504541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test lc_ctrl_jtag_errors has 1 failures.

17.lc_ctrl_jtag_errors.38610390001476754855775117096697760736923287917122913396995837752017294355628
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_jtag_errors/latest/run.log

  [make]: simulate
  cd /workspace/17.lc_ctrl_jtag_errors/latest && /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658743980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_errors.1658743980
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 17 12:48 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.lc_ctrl_stress_all_with_rand_reset.91888995500084166706106622825067678298708393329809823829081890174946237455099
    Line 14281, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21197743537 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 21197743537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.lc_ctrl_stress_all_with_rand_reset.74711388968711675164208575159882371949109646137984041478532816050956099120455
    Line 801, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1143151675 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1818081979 [0x6c5dbabb]) Regname: lc_ctrl_reg_block.transition_token_2 reset value: 0x0
  UVM_INFO @ 1143151675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```