LC_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.940s	429.047us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	42.399us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	110.549us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.570s	281.361us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.420s	37.439us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.770s	40.194us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	110.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	37.439us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	state_post_trans	lc_ctrl_state_post_trans	11.990s	834.500us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.330s	424.529us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	14.070us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.090s	1.093ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.860s	2.271ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_prog_failure	5.090s	1.093ms	50	50	100.00
		lc_ctrl_errors	22.860s	2.271ms	50	50	100.00
		lc_ctrl_security_escalation	17.530s	2.164ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.843m	4.114ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.320s	4.416ms	20	20	100.00
		lc_ctrl_jtag_errors	1.648m	11.688ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.170s	899.927us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.740s	2.440ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.320s	4.416ms	20	20	100.00
		lc_ctrl_jtag_errors	1.648m	11.688ms	20	20	100.00
		lc_ctrl_jtag_access	22.970s	1.831ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.280s	1.274ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.410s	486.240us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.790s	91.369us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.880s	1.084ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.900s	2.034ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.710s	207.836us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.850s	836.950us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.250s	108.589us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.520s	2.341ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.060s	34.287us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.059m	67.645ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.310s	81.124us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	498.129us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	498.129us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	42.399us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	110.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	37.439us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	162.864us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	42.399us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	110.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	37.439us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	162.864us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
		lc_ctrl_tl_intg_err	11.110s	1.926ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	11.110s	1.926ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.330s	424.529us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.390s	1.375ms	50	50	100.00
		lc_ctrl_sec_cm	38.080s	1.299ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.530s	2.164ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.990s	834.500us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.740s	2.440ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.900s	1.411ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.900s	1.411ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.620s	1.052ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.800s	1.182ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.800s	1.182ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	7.544m	72.214ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.97	97.29	95.61	91.98	97.67	95.93	98.48	94.82

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.38572564221184051326598351510431436013085157370958447180197898630391007217201
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:5f39fa4e-b333-46ce-8b7d-79eeb271fe56
      

    • 3.lc_ctrl_stress_all_with_rand_reset.43732841214520378309285426405024431132378541220200349463639873849233157124204
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f3072dff-c942-4bda-8113-b1f01d9cb873
      

    • ... and 27 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 12 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.18434811464845710179166855028842767734140212080086089114026131575540853463029
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:581ddcec-6dff-4243-842d-5cd1af8e1dfa
      

    • 9.lc_ctrl_stress_all_with_rand_reset.22923461418012034832757755472692977820188643800847848282061986215716555727899
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:cd1e61eb-d93d-4a48-bc2f-6344fee7e7ad
      

    • ... and 10 more failures.

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.2303557291633698202572242863709682007019470357886522371241203849254599381163
      Line 18051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19102771651 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 19102771651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.37968868218188394134083397588786126340691863289725502682418101261157089897179
      Line 769, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1242101393 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 1242101393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test lc_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 17.lc_ctrl_csr_mem_rw_with_rand_reset.71928510653867197170433584339266931704217572313344545180131181774906133180057
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        Job ID: smart:2364339d-2818-4e2e-b28b-a3cc197b9272
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.13116281649157542802264533929629035574077137127499389360567274516296481716386
      Line 1082, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3625425521 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked1
        UVM_INFO @ 3625425521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.34687499326682827121649190892694026620409750743937444232176414407127880433024
      Line 5575, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4945149276 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4945149276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.01.18_08.39.09
• 2024.01.15_03.56.36
• 2024.01.11_03.10.52
• 2024.01.08_02.57.45
• 2024.01.04_01.22.04
• 2024.01.01_00.49.32