LC_CTRL Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.760s	1.420ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	16.093us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	18.837us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.570s	340.573us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.050s	50.519us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.450s	59.183us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	18.837us	20	20	100.00
		lc_ctrl_csr_aliasing	1.050s	50.519us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.110s	208.555us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.440s	4.785ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.470us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.160s	160.871us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.860s	968.121us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_prog_failure	5.160s	160.871us	50	50	100.00
		lc_ctrl_errors	26.860s	968.121us	50	50	100.00
		lc_ctrl_security_escalation	15.810s	459.526us	49	50	98.00
		lc_ctrl_jtag_state_failure	1.538m	5.559ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.500s	2.569ms	19	20	95.00
		lc_ctrl_jtag_errors	1.542m	14.066ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.600s	1.917ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.300s	572.422us	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.500s	2.569ms	19	20	95.00
		lc_ctrl_jtag_errors	1.542m	14.066ms	20	20	100.00
		lc_ctrl_jtag_access	24.160s	1.046ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.280s	3.241ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.660s	155.700us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.190s	800.441us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.450s	2.674ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.510s	933.563us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	146.910us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.260s	110.498us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.350s	284.492us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.000s	4.104ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	14.699us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.671m	143.978ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.420s	31.234us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.080s	405.490us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.080s	405.490us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	16.093us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.837us	20	20	100.00
		lc_ctrl_csr_aliasing	1.050s	50.519us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.220s	55.239us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	16.093us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.837us	20	20	100.00
		lc_ctrl_csr_aliasing	1.050s	50.519us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.220s	55.239us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	786.540us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	786.540us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.440s	4.785ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.800s	1.448ms	50	50	100.00
		lc_ctrl_sec_cm	41.680s	232.027us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.810s	459.526us	49	50	98.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.110s	208.555us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.300s	572.422us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.120s	1.318ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.120s	1.318ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.830s	1.239ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.460s	695.647us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.460s	695.647us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	21.986m	10.671ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			981	1030	95.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.38	97.29	95.70	91.98	100.00	95.93	98.73	95.00

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.102257839575658577265446664848888348458151810434625003321224779494479550087639
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:ded0afd7-2434-453f-bd09-3e64a6de6a4b
      

    • 1.lc_ctrl_stress_all_with_rand_reset.114791540895555568793434515009737003170891018317130369791927339202628029155837
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:9fed662b-2c06-4118-9e8c-474da9225455
      

    • ... and 23 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 7 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.86848518307098667981627263806896079831441655728629239212244145629201986939373
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d257f5c7-d17e-448b-8c5d-9bc56dd05ea9
      

    • 26.lc_ctrl_stress_all_with_rand_reset.101884635967295129448276361525218408355550241418551689211846958480126463480561
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:99a53107-dc11-48d5-b4a0-deb51063e64c
      

    • ... and 5 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.80577631737138940926093853320188167645162816289413795176267643186126415006453
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   8263382 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x94220200
        UVM_INFO @   8263382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.lc_ctrl_stress_all_with_rand_reset.36642849970922755423555203337611236794594276755667525136733764543800569790592
      Line 23913, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 92791245699 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x7000eeec
        UVM_INFO @ 92791245699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.37843342122239965602600269971496875613174361770040343613555460125965237712599
      Line 6860, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23188266028 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23188266028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.lc_ctrl_stress_all_with_rand_reset.39123361270634098793282010238498361292546055842766420141498190819807209619070
      Line 9164, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14024021928 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14024021928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 13.lc_ctrl_stress_all.107912522480662627646355205883253186446934571037358182463067767461854931317651
      Line 13993, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8043053127 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8043053127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.87238231898749079127019811854791516373935477874620686746256872634729140486947
      Line 6793, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10448588279 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked6
        UVM_INFO @ 10448588279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.lc_ctrl_stress_all_with_rand_reset.90666268259097140934585921774595989196313582428857698231704515256363373393501
      Line 7833, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6001437215 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked3
        UVM_INFO @ 6001437215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.40627539619724894838142974999360390641671257372816843018675816522434095829582
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1e15ff14-927f-4fa3-9849-3cc273d964a5
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test lc_ctrl_jtag_prog_failure has 1 failures.

    • 3.lc_ctrl_jtag_prog_failure.51808625369787801778963841195286016891161403632478067669294100824772405891143
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest/run.log

        Job ID: smart:15dc31c0-d92f-4e9c-b4b8-e5e116ec6811
      

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.19656073118945996317212368703977926741728270656938633805053111225422600388791
      Line 34721, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 98553926300 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 98553926300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.53971382569391061339353298988616393741146498562816105907389105756669421380740
      Line 20509, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80384047743 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 80384047743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.15120523786497574251390706917421782431785002905369262508162480447892023568150
      Line 917, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5558442954 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 2019143304 [0x7859ae88]) Regname: lc_ctrl_reg_block.transition_token_2 reset value: 0x0
        UVM_INFO @ 5558442954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.53660763843060925882513292159974759627917609630107281644218008852590666223606
      Line 23090, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test lc_ctrl_security_escalation has 1 failures.

    • 48.lc_ctrl_security_escalation.56132641008571477151933902999893264455366459342782398986759308310546440974479
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_security_escalation/latest/run.log

        Job ID: smart:5a7c5369-729f-478b-9783-e2098110a664
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.104912850241237563614814381533515331157526109395755158746948026205435888741825
      Line 4842, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 628762405 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 628762405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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