4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
| V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
| V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
| lc_ctrl_errors | 0 | 50 | 0.00 | ||||
| lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
| lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
| lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_hw_reset | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_rw | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_bit_bash | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_aliasing | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_same_csr_outstanding | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0 | 10 | 0.00 | ||||
| lc_ctrl_jtag_alert_test | 0 | 10 | 0.00 | ||||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
| V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 700 | 0.00 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
| lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 0 | 175 | 0.00 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1030 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 27 | 27 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1032 failures:
0.lc_ctrl_smoke.76591028455260885184709097907661733116872551237144078384789371166372505301541
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.86878252498123874502569918900359422584149079454904040335137846172387865056766
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.52930659320206694397387510999331567625405023327281220082857144309014506995077
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.113830112148924571886202234433575376732859875519513696653282732210792408064446
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.95381855634680139646129423654797832485648778531019797853572001808894032892756
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.64485694068472002889612886713755081395122794409843831182153623471227208785951
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.66514323772205200110805835766769680163278630310574536547120134632304813578631
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.25089124438671754960594776356102496131571285689418638937983006281074916465662
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.62690981198726877265512499236792544992492536136709885391255949540174701599429
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.108164424624448673638225857260602101448520453650464624220757684292235554310001
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.