LC_CTRL Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.670s	366.649us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.050s	59.832us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	59.756us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.780s	48.604us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.310s	35.069us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.940s	135.761us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	59.756us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	35.069us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.180s	765.753us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.350s	2.214ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	10.330us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.500s	110.454us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.780s	2.020ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_prog_failure	4.500s	110.454us	50	50	100.00
		lc_ctrl_errors	25.780s	2.020ms	50	50	100.00
		lc_ctrl_security_escalation	15.490s	1.637ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.131m	8.277ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.230s	1.260ms	20	20	100.00
		lc_ctrl_jtag_errors	1.391m	12.317ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.580s	795.690us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.960s	6.302ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.230s	1.260ms	20	20	100.00
		lc_ctrl_jtag_errors	1.391m	12.317ms	20	20	100.00
		lc_ctrl_jtag_access	30.600s	1.468ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.580s	6.302ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.490s	170.938us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.010s	104.918us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.860s	6.846ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.460s	713.018us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	182.178us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.260s	468.776us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.000s	110.401us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	37.840s	1.737ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	28.115us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.518m	27.437ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.220s	86.487us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.070s	100.585us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.070s	100.585us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.050s	59.832us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	59.756us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	35.069us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	61.004us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.050s	59.832us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	59.756us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	35.069us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	61.004us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.530s	109.516us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.530s	109.516us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.350s	2.214ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.870s	658.033us	50	50	100.00
		lc_ctrl_sec_cm	40.320s	2.256ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.490s	1.637ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.180s	765.753us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.960s	6.302ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.380s	1.024ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.380s	1.024ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.390s	2.490ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.080s	780.915us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.080s	780.915us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	18.820m	133.296ms	2	50	4.00
V3		TOTAL			2	50	4.00
		TOTAL			982	1030	95.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	97.29	95.78	91.98	97.67	96.13	98.73	94.82

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.31073714188228705081683889861575198307279092494388983398118447270769290005931
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:b56114f8-0662-453f-8ec1-25a40c347bc4
      

    • 1.lc_ctrl_stress_all_with_rand_reset.80640635268424723234377470843390904961486400235825182864013904554827794867033
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:b7c19a50-29b2-4e01-87f5-8d61363744f1
      

    • ... and 25 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 11 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.19776114617050721758682901627308926414888232835730251882852455387559852890334
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:c093de15-012e-4d76-a39a-544a8b993230
      

    • 17.lc_ctrl_stress_all_with_rand_reset.53679341058443469958496737129079849312424429054412151768361569301022456190507
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:c3df14ed-63b4-4742-a0f5-1180e120a4ef
      

    • ... and 9 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.22223685128106864068514605750781842039490545755444451093174533178945002519071
      Line 19368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 69408088459 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x24359200
        UVM_INFO @ 69408088459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.37733239856229339957434278311957784095944529836700730095952967198255218744246
      Line 15864, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 60631298680 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x43ec161c
        UVM_INFO @ 60631298680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.14275216582414800878482423616073479718077069385015690050461707747994034185951
      Line 36230, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 126858887671 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 126858887671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.22579975561549803266066233701751295232954219243406867952949620357174009831141
      Line 30984, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 133296426157 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 133296426157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:237) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProd has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.26764059281041164671720295848736419764237053608211807424279027930563224414686
      Line 10424, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38398647918 ps: (lc_ctrl_scoreboard.sv:237) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStProd
        UVM_INFO @ 38398647918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.22453966937837755107865083138960000641259460454879512958236260695982763391550
      Line 9331, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75069225606 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 75069225606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.72361510129478589106070764085288870435590118642185673434096634069514352058813
      Line 35912, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32825059019 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1037779569 [0x3ddb4271]) Regname: lc_ctrl_reg_block.transition_token_3 reset value: 0x0
        UVM_INFO @ 32825059019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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