LC_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.000s	224.235us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.030s	55.476us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.020s	25.746us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.970s	50.480us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.540s	57.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.190s	137.165us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.020s	25.746us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	57.059us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.500s	78.969us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	15.120s	376.571us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	21.626us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.230s	474.411us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.420s	4.325ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_prog_failure	5.230s	474.411us	50	50	100.00
		lc_ctrl_errors	26.420s	4.325ms	50	50	100.00
		lc_ctrl_security_escalation	21.090s	2.548ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.664m	2.815ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.380s	644.364us	20	20	100.00
		lc_ctrl_jtag_errors	1.801m	4.035ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.540s	428.180us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.740s	1.884ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.380s	644.364us	20	20	100.00
		lc_ctrl_jtag_errors	1.801m	4.035ms	20	20	100.00
		lc_ctrl_jtag_access	23.370s	1.946ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.970s	2.411ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.840s	285.387us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.130s	959.967us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.310s	1.461ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.960s	3.011ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.760s	35.681us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.150s	124.042us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.320s	116.959us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.890s	617.839us	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	26.598us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.775m	24.429ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.550s	158.931us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.630s	1.651ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.630s	1.651ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.030s	55.476us	5	5	100.00
		lc_ctrl_csr_rw	1.020s	25.746us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	57.059us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	286.943us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.030s	55.476us	5	5	100.00
		lc_ctrl_csr_rw	1.020s	25.746us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	57.059us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	286.943us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
		lc_ctrl_tl_intg_err	4.810s	136.662us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.810s	136.662us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	15.120s	376.571us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.610s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	37.630s	229.445us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.090s	2.548ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.500s	78.969us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.740s	1.884ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.190s	912.632us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.190s	912.632us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.960s	14.885ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.150s	2.449ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.150s	2.449ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.114h	253.089ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.43	97.29	95.96	91.98	100.00	96.13	98.48	95.18

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.34073344969569104345512703069777782282548775044572098790713547877231690446670
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f05ccfdb-a45e-45b5-b015-1a3d66e3103e
      

    • 1.lc_ctrl_stress_all_with_rand_reset.47090665626367744470765390557231164773530538246355482759732754583806642941471
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:0f03b4d0-4bdb-40be-99bf-bd7ab9026d7d
      

    • ... and 18 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 11 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.95483150328306733092940072316062006843885870290791998248434311488446302278643
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:0c41e1e6-e948-4e47-98ad-a712c539c6dd
      

    • 13.lc_ctrl_stress_all_with_rand_reset.1728839302574939625744494294837913157874690990876840825014322696071542852798
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:4f423223-8b51-4934-a04a-e0535302bdca
      

    • ... and 9 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.56326366682422562164704537340533776526576130564772284934392244903788027835623
      Line 5109, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 13348263147 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x277afdbc
        UVM_INFO @ 13348263147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.74119317077124554606646594660198673340932026292194411458876673723000355087723
      Line 5754, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 19455076631 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xd25c0800
        UVM_INFO @ 19455076631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.49723730145520136854529016704415356469353452844963357540633582958322305082645
      Line 328, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 207882177 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
        UVM_INFO @ 207882177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 7.lc_ctrl_jtag_priority.39271791760076650863134348430030745369989981479549280867957711416581546199964
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10011411932 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10011411932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.17031459518481829368921474389211911633689372549600423843578158189482483301181
      Line 15000, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9889965919 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1856098535 [0x6ea1d0e7]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: 0x0
        UVM_INFO @ 9889965919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.74782305198135408987539462019615319953076862918590638309175457816412099723090
      Line 18799, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 86995883058 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked5
        UVM_INFO @ 86995883058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.02.05_04.44.04
• 2024.01.31_20.53.30
• 2024.01.25_17.44.53
• 2024.01.22_10.59.35
• 2024.01.18_08.39.09
• 2024.01.15_03.56.36