LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.250s	324.729us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset			0	5	0.00
V1	csr_rw	lc_ctrl_csr_rw			0	20	0.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash			0	5	0.00
V1	csr_aliasing	lc_ctrl_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
V1		TOTAL			50	105	47.62
V2	state_post_trans	lc_ctrl_state_post_trans	11.680s	92.203us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.310s	1.070ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.977us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.530s	111.675us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.710s	22.513ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_prog_failure	4.530s	111.675us	50	50	100.00
		lc_ctrl_errors	25.710s	22.513ms	50	50	100.00
		lc_ctrl_security_escalation	17.370s	504.737us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.420m	2.147ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.670s	532.485us	20	20	100.00
		lc_ctrl_jtag_errors	1.511m	13.268ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.560s	686.829us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.760s	2.948ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.670s	532.485us	20	20	100.00
		lc_ctrl_jtag_errors	1.511m	13.268ms	20	20	100.00
		lc_ctrl_jtag_access	24.730s	2.102ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.590s	1.459ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset			0	10	0.00
		lc_ctrl_jtag_csr_rw			0	10	0.00
		lc_ctrl_jtag_csr_bit_bash			0	10	0.00
		lc_ctrl_jtag_csr_aliasing			0	10	0.00
		lc_ctrl_jtag_same_csr_outstanding			0	10	0.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset			0	10	0.00
		lc_ctrl_jtag_alert_test			0	10	0.00
V2	jtag_priority	lc_ctrl_jtag_priority	17.620s	729.389us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.450s	20.466us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.248m	19.494ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.500s	67.727us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors			0	20	0.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset			0	5	0.00
		lc_ctrl_csr_rw			0	20	0.00
		lc_ctrl_csr_aliasing			0	5	0.00
		lc_ctrl_same_csr_outstanding			0	20	0.00
V2		TOTAL			589	700	84.14
V2S	tl_intg_err	lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
		lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err			0	20	0.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.310s	1.070ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.780s	1.434ms	50	50	100.00
		lc_ctrl_sec_cm	37.780s	777.504us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.370s	504.737us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.680s	92.203us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.760s	2.948ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.230s	1.771ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.230s	1.771ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	32.680s	2.554ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.340s	3.083ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.340s	3.083ms	50	50	100.00
V2S		TOTAL			155	175	88.57
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.250h	129.830ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			812	1030	78.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	1	16.67
V2	27	27	17	62.96
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.79	95.62	93.30	100.00	98.34	99.00	96.25

Failure Buckets

• Job killed most likely because its dependent job failed. has 185 failures:

  • Test lc_ctrl_jtag_csr_hw_reset has 10 failures.

    • 0.lc_ctrl_jtag_csr_hw_reset.22262449370573721751149475012382445904924083617582762306503183765248042498949
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest/run.log

    • 1.lc_ctrl_jtag_csr_hw_reset.11086240494544759004606819658146826786764099322059982140622706447513171805181
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_rw has 10 failures.

    • 0.lc_ctrl_jtag_csr_rw.107815318810721768569649505293764085231576527870837575952597768394706143590198
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest/run.log

    • 1.lc_ctrl_jtag_csr_rw.71959966332858629956803012670463536880790960659126212149906960158850780374800
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_bit_bash has 10 failures.

    • 0.lc_ctrl_jtag_csr_bit_bash.36602275318938230649895749766338080528525841754170287663211420247229768333073
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest/run.log

    • 1.lc_ctrl_jtag_csr_bit_bash.112865397740029012357420227934511143919569547652933560403562577418134979144211
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_csr_aliasing has 10 failures.

    • 0.lc_ctrl_jtag_csr_aliasing.95338179638153142600052610903902414744551364492947292187379946217365661608363
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest/run.log

    • 1.lc_ctrl_jtag_csr_aliasing.14337436298874418584236113269838664421614641014169700546543834668943108819379
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest/run.log

    • ... and 8 more failures.

  • Test lc_ctrl_jtag_same_csr_outstanding has 10 failures.

    • 0.lc_ctrl_jtag_same_csr_outstanding.110343192635005472555420495168876399193864029576593035069122397481241931924019
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest/run.log

    • 1.lc_ctrl_jtag_same_csr_outstanding.109507484964626154842955459778131260037105163648175887088110597627139789588336
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest/run.log

    • ... and 8 more failures.

  • ... and 10 more tests.

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.35667568162901287813492525280573802117619580714350894185082287515888674827712
      Line 21082, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11625631785 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11625631785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.2838996374268282921852521782957085325052118485718197353897974517838656089949
      Line 11191, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49980151696 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 49980151696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.109459788687599084248917024002408247804418211148101579471375813714620993822502
      Line 40337, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27268984816 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 27268984816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_stress_all_with_rand_reset.23605692224824295462766149566174875722304008985252366899070562058697419802167
      Line 26440, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26668327500 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 26668327500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.56249568627156916921957286753005251702780610151894880480102148889026781142968
      Line 6021, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21698488859 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 21698488859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.18903800587129068870932228410414876633622151734924902781607705320929788642531
      Line 3586, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5970164134 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5970164134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• tar (child): /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:

  • Test cover_reg_top has 1 failures.
    • cover_reg_top
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cover_reg_top/build.log

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.80807353684766791513381308525061338675279525944577215849219097727395084894085
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:974d6b6b-4551-4cd7-8d35-f7184c155f51
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 13.lc_ctrl_stress_all.1250779819465222222398487594935396902033284117856540703510935044064704796575
      Line 1921, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1143398200 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1143398200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.96146225210121446733302834086136494350280792240769639218460395964974258427571
      Line 16995, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6763912293 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 6763912293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.20_03.41.04
• 2024.03.20_03.39.59
• 2024.03.18_04.37.37
• 2024.03.18_04.36.41
• 2024.03.15_00.11.15
• 2024.03.15_00.10.22