LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.510s	223.603us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	41.617us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	15.911us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.870s	27.052us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.420s	17.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.040s	34.000us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	15.911us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	17.510us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.140s	225.632us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.860s	4.628ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	21.931us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.340s	395.528us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.050s	1.947ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_prog_failure	5.340s	395.528us	50	50	100.00
		lc_ctrl_errors	21.050s	1.947ms	50	50	100.00
		lc_ctrl_security_escalation	16.490s	435.394us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.653m	4.169ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.660s	2.014ms	20	20	100.00
		lc_ctrl_jtag_errors	1.308m	3.082ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.730s	5.350ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.530s	3.006ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.660s	2.014ms	20	20	100.00
		lc_ctrl_jtag_errors	1.308m	3.082ms	20	20	100.00
		lc_ctrl_jtag_access	17.540s	3.148ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.310s	1.319ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.730s	631.397us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.330s	326.938us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.000s	10.437ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.820s	996.640us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	48.849us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.710s	391.414us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.000s	92.427us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.890s	3.161ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.530s	118.670us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	13.805m	41.524ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.480s	117.180us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.940s	124.620us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.940s	124.620us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	41.617us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	15.911us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	17.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	45.952us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	41.617us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	15.911us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	17.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	45.952us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
		lc_ctrl_tl_intg_err	5.130s	160.377us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.130s	160.377us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.860s	4.628ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.360s	633.379us	50	50	100.00
		lc_ctrl_sec_cm	40.990s	865.649us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.490s	435.394us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.140s	225.632us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.530s	3.006ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.400s	694.851us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.400s	694.851us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.000s	777.792us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.490s	705.938us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.490s	705.938us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.987h	23.636ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.71914798545968459599702456782316143288195499307822405274984244348960172761298
      Line 4517, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2312143774 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2312143774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.75074750320211731192458589807599614120274650170544796371251333655127984080745
      Line 25469, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33920619949 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 33920619949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.30297302269830633736937673760094271152372212762097414617592995131529934662011
      Line 39171, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 29.lc_ctrl_stress_all_with_rand_reset.71559267662719046219111840668579439194486293360339795429349112092274725558516
      Line 36890, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.34510838850691573979665894926694355432964695704421079753810399731772446943519
      Line 47378, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107810734907 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 107810734907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.lc_ctrl_stress_all_with_rand_reset.97745240051012529146923507089130247665386843294730038498758618020715535461121
      Line 42013, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 260203552931 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 260203552931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.76407209019595010255222839095684036718901217496546842151281241023494950194074
      Line 16074, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 454218809337 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 454218809337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.106302375963309499351648021412124676372453488981923432672954741380361657857959
      Line 31190, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66973522598 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 66973522598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 40.lc_ctrl_volatile_unlock_smoke.112552812297995438698570754563924322729174306927714680455022623211147801558265
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 114965794 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x47eed304) == 0x1
        UVM_INFO @ 114965794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.83731584708964766103461628564191976130215415099074369169296692408155678471286
      Line 15563, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76652628419 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 76652628419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.37845339809761064952691063430707769198483365212184836602189426771991802763326
      Line 20847, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20293671957 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 20293671957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:71d80cbb-2137-4422-a97f-6d62b994a9d4
      

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