LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.910s	213.353us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	15.217us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	55.832us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.710s	67.570us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.820s	142.758us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.670s	30.145us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	55.832us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	142.758us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.920s	98.887us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.760s	2.921ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	24.304us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.720s	477.524us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.990s	866.468us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_prog_failure	5.720s	477.524us	50	50	100.00
		lc_ctrl_errors	23.990s	866.468us	50	50	100.00
		lc_ctrl_security_escalation	16.090s	746.572us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.229m	9.106ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.130s	3.440ms	20	20	100.00
		lc_ctrl_jtag_errors	1.963m	33.332ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.350s	681.146us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.390s	920.852us	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.130s	3.440ms	20	20	100.00
		lc_ctrl_jtag_errors	1.963m	33.332ms	20	20	100.00
		lc_ctrl_jtag_access	26.580s	3.780ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.060s	2.336ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.390s	406.721us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.650s	1.203ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.360s	5.078ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.220s	1.501ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.960s	41.141us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.970s	446.464us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.130s	424.796us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	24.070s	3.801ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.180s	13.993us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.111m	16.023ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.560s	414.068us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.550s	140.223us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.550s	140.223us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	15.217us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	55.832us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	142.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	284.150us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	15.217us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	55.832us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	142.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	284.150us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.200s	190.055us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.200s	190.055us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.760s	2.921ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.380s	340.364us	50	50	100.00
		lc_ctrl_sec_cm	37.020s	1.137ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.090s	746.572us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.920s	98.887us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.390s	920.852us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.100s	12.048ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.100s	12.048ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.100s	509.085us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.050s	598.271us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.050s	598.271us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	29.103m	495.948ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.82	96.03	93.31	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.89408179120721365825461122017488324939218646129097189281393823200923302042461
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1786700123 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1786700123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.67477083314080974744957293074526863556870953613746741356428989991597864397591
      Line 24243, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 175588282967 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 175588282967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.8232678629675443584627461300103061847238482883801974738077396605251609398173
      Line 14730, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21231097822 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 21231097822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.82079532714800876260383775545849968530918390720157616641387116976229451570207
      Line 21715, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69922021111 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 69922021111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 37.lc_ctrl_stress_all.78083293695056143621623646502732169747616073698599421317244217838903059160184
      Line 5187, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5024757742 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5024757742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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