LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.480s	1.115ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.700s	21.492us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.600s	15.739us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	225.413us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.200s	34.134us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.550s	57.139us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.600s	15.739us	20	20	100.00
		lc_ctrl_csr_aliasing	2.200s	34.134us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.200s	82.208us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.990s	631.706us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.470s	10.592us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.800s	140.796us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.310s	2.807ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_prog_failure	7.800s	140.796us	50	50	100.00
		lc_ctrl_errors	28.310s	2.807ms	49	50	98.00
		lc_ctrl_security_escalation	23.950s	2.109ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.765m	2.822ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.200s	4.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.216m	2.131ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.540s	308.250us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.750s	1.096ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.200s	4.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.216m	2.131ms	20	20	100.00
		lc_ctrl_jtag_access	27.900s	7.071ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.470s	1.775ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.860s	4.901ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.670s	73.414us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	33.590s	12.860ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.100s	661.693us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.050s	139.623us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.240s	240.010us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.580s	288.861us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.940s	2.451ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.660s	32.511us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.657m	43.307ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.120s	31.285us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	7.030s	1.004ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	7.030s	1.004ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.700s	21.492us	5	5	100.00
		lc_ctrl_csr_rw	1.600s	15.739us	20	20	100.00
		lc_ctrl_csr_aliasing	2.200s	34.134us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.230s	41.385us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.700s	21.492us	5	5	100.00
		lc_ctrl_csr_rw	1.600s	15.739us	20	20	100.00
		lc_ctrl_csr_aliasing	2.200s	34.134us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.230s	41.385us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
		lc_ctrl_tl_intg_err	4.900s	983.543us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.900s	983.543us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.990s	631.706us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.260s	406.354us	50	50	100.00
		lc_ctrl_sec_cm	40.730s	358.587us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	23.950s	2.109ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.200s	82.208us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.750s	1.096ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.230s	870.966us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.230s	870.966us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.990s	996.079us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.390s	2.247ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.390s	2.247ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.293m	22.102ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.90	95.38	93.40	100.00	98.49	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.3901022503804953650487659166257104003136773844969198699964154433747627818408
      Line 13785, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4903598721 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4903598721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.8828170377905616609466709230710699780658782331157661732416622266622677248627
      Line 149, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 339898621 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 339898621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.45195153271610801758064865766528351964260228506683224169989114970361253100266
      Line 2776, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2761307679 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2761307679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 24.lc_ctrl_errors.111308338490246381446641731201664033514358344112876688607656150158262365249885
      Line 1187, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 390457332 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 390457332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.85876622517123395396563320016698175663439120952168860709744106594703198179007
      Line 4935, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1543632671 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1543632671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.19_09.04.56
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• 2024.09.10_08.11.26
• 2024.09.05_04.20.58
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