LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.440s	254.918us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.860s	75.876us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.680s	18.107us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.870s	71.470us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.880s	32.798us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.170s	28.018us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.680s	18.107us	20	20	100.00
		lc_ctrl_csr_aliasing	1.880s	32.798us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.310s	368.714us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	30.710s	1.557ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.530s	13.373us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.520s	452.088us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.380s	525.013us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_prog_failure	6.520s	452.088us	50	50	100.00
		lc_ctrl_errors	22.380s	525.013us	50	50	100.00
		lc_ctrl_security_escalation	20.160s	374.411us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.003m	8.551ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.660s	3.066ms	20	20	100.00
		lc_ctrl_jtag_errors	2.044m	83.267ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.500s	2.618ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	42.030s	1.230ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.660s	3.066ms	20	20	100.00
		lc_ctrl_jtag_errors	2.044m	83.267ms	20	20	100.00
		lc_ctrl_jtag_access	29.710s	2.210ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	50.340s	1.330ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.010s	199.577us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.410s	174.814us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.020s	17.475ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.330s	1.146ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.480s	38.135us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.830s	948.288us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.350s	75.558us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.210m	2.878ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.880s	17.711us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.312m	28.463ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.990s	45.666us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	675.585us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	675.585us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.860s	75.876us	5	5	100.00
		lc_ctrl_csr_rw	1.680s	18.107us	20	20	100.00
		lc_ctrl_csr_aliasing	1.880s	32.798us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	91.379us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.860s	75.876us	5	5	100.00
		lc_ctrl_csr_rw	1.680s	18.107us	20	20	100.00
		lc_ctrl_csr_aliasing	1.880s	32.798us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	91.379us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
		lc_ctrl_tl_intg_err	5.230s	77.443us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.230s	77.443us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	30.710s	1.557ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.390s	2.199ms	50	50	100.00
		lc_ctrl_sec_cm	30.580s	713.679us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.160s	374.411us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.310s	368.714us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	42.030s	1.230ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	30.030s	3.224ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	30.030s	3.224ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.740s	1.194ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.900s	2.665ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.900s	2.665ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.615m	12.784ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1011	1030	98.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.98	97.90	96.12	93.40	97.62	98.49	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 15 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.96065682973463100956363327794458333828836894483902059166663479277148110874477
      Line 1736, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5252910037 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5252910037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.70568815368053652406064708157167872438554809084502889697587298254134162252239
      Line 4794, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2869960108 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2869960108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.75552274020297078448381103257799027254790831374824714149980087001447889750756
      Line 7389, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2760816720 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2760816720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.8343573941989617285203589848876422172176759782819887542911101605177281870337
      Line 359, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 348093327 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 348093327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.91144467313605066959945175748094974285246892961175380928796475832702793261590
      Log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 47.lc_ctrl_stress_all.92287865992623933255038498800944006942453436210590339608932549158898395255677
      Line 12736, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2155530162 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2155530162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.25_11.01.11
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