LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.530s	82.415us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.600s	113.683us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.750s	16.728us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.780s	95.361us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.990s	77.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	3.860s	32.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.750s	16.728us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	77.269us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	16.440s	204.819us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.980s	648.440us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.560s	14.674us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.010s	117.872us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	31.550s	1.927ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_prog_failure	7.010s	117.872us	50	50	100.00
		lc_ctrl_errors	31.550s	1.927ms	50	50	100.00
		lc_ctrl_security_escalation	23.540s	1.738ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.442m	14.040ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	44.060s	5.029ms	20	20	100.00
		lc_ctrl_jtag_errors	2.194m	64.617ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.550s	2.023ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.140s	4.701ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	44.060s	5.029ms	20	20	100.00
		lc_ctrl_jtag_errors	2.194m	64.617ms	20	20	100.00
		lc_ctrl_jtag_access	33.030s	1.104ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.020s	4.237ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.110s	590.933us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.450s	164.134us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.560s	4.558ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	32.930s	5.555ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	3.290s	46.892us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.090s	1.868ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.490s	1.336ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.670s	1.766ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.920s	17.865us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.591m	24.387ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.220s	27.271us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.420s	159.347us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.420s	159.347us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.600s	113.683us	5	5	100.00
		lc_ctrl_csr_rw	1.750s	16.728us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	77.269us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.950s	192.072us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.600s	113.683us	5	5	100.00
		lc_ctrl_csr_rw	1.750s	16.728us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	77.269us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.950s	192.072us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
		lc_ctrl_tl_intg_err	5.120s	79.222us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.120s	79.222us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.980s	648.440us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.030s	172.708us	50	50	100.00
		lc_ctrl_sec_cm	39.680s	800.507us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	23.540s	1.738ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	16.440s	204.819us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.140s	4.701ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.830s	401.576us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.830s	401.576us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.390s	2.106ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.900s	643.489us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.900s	643.489us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.823m	18.101ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.90	96.03	93.40	97.62	98.49	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.111233565382681346545781933810616180817064290860037353588411868634359270076583
      Line 2916, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7534378708 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7534378708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.42324378313426287090951083784162526021962295567545042859058954393601294543010
      Line 1909, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 753396764 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 753396764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.29644310418918246277470090571925725662716665488756230509155645591288325685423
      Line 4888, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2391318872 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2391318872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.18556671648990205988141679905236660670246190360749420806334697357656575817688
      Line 3471, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1793598092 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1793598092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
  • Test lc_ctrl_stress_all has 1 failures.

    • 33.lc_ctrl_stress_all.49733016611976067671279431495927821947728301365465523742476898987539876234352
      Line 3394, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1428039354 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1428039354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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