LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.530s	465.828us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.790s	20.178us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.510s	18.661us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.260s	153.419us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.210s	34.877us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.410s	96.146us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.510s	18.661us	20	20	100.00
		lc_ctrl_csr_aliasing	2.210s	34.877us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.170s	91.927us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	32.410s	5.521ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.530s	11.350us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.280s	207.531us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	29.220s	2.114ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_prog_failure	6.280s	207.531us	50	50	100.00
		lc_ctrl_errors	29.220s	2.114ms	50	50	100.00
		lc_ctrl_security_escalation	23.420s	759.392us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.115m	14.882ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.030s	820.805us	20	20	100.00
		lc_ctrl_jtag_errors	1.351m	15.750ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.300s	2.427ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.120s	4.005ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.030s	820.805us	20	20	100.00
		lc_ctrl_jtag_errors	1.351m	15.750ms	20	20	100.00
		lc_ctrl_jtag_access	20.500s	3.603ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.130s	1.419ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.670s	104.898us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.900s	99.332us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.240s	3.598ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.390s	3.308ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.250s	160.391us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.980s	148.765us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.470s	114.530us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	59.660s	2.093ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.690s	22.029us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.893m	45.818ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.940s	23.661us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.960s	415.058us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.960s	415.058us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.790s	20.178us	5	5	100.00
		lc_ctrl_csr_rw	1.510s	18.661us	20	20	100.00
		lc_ctrl_csr_aliasing	2.210s	34.877us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.210s	50.982us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.790s	20.178us	5	5	100.00
		lc_ctrl_csr_rw	1.510s	18.661us	20	20	100.00
		lc_ctrl_csr_aliasing	2.210s	34.877us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.210s	50.982us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
		lc_ctrl_tl_intg_err	5.360s	496.258us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.360s	496.258us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	32.410s	5.521ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.770s	314.562us	50	50	100.00
		lc_ctrl_sec_cm	50.230s	977.966us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	23.420s	759.392us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.170s	91.927us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.120s	4.005ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.370s	396.402us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.370s	396.402us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	33.880s	862.167us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.770s	2.077ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.770s	2.077ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.546m	23.274ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	97.90	96.12	93.40	100.00	98.49	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 25 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.107305036147657575480430480626408330825800884663961479943599939581671262906733
    Line 2782, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1695412287 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1695412287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.6486516479458348290313320467693554997655762177129634358701187142982692283541
    Line 2170, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1160018156 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1160018156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.lc_ctrl_stress_all_with_rand_reset.11685231737029313409712718769428680712858580814338950288955686911573818630845
    Line 1099, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2295338587 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 2295338587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.lc_ctrl_stress_all_with_rand_reset.54229396945931840727244975355402288696011473287602681126073918807671713881550
    Line 6821, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10772132756 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 10772132756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:
- Test lc_ctrl_jtag_priority has 1 failures.
  - 5.lc_ctrl_jtag_priority.49049473909873697920603502873086829092700768348890348547103464050537597743335
    Line 490, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest/run.log
```
  UVM_FATAL @ 10003543709 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
  UVM_INFO @ 10003543709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:240) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStDev has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.lc_ctrl_stress_all_with_rand_reset.111692550631479889390004910013680385309915285713238044125244027343113987113813
    Line 3943, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20365794832 ps: (lc_ctrl_scoreboard.sv:240) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStDev
  UVM_INFO @ 20365794832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.lc_ctrl_stress_all_with_rand_reset.22441824423794357629179663804390771341456061179025755317912180359657016257381
    Line 1989, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1435922064 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 1435922064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`