LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.100s	480.972us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.420s	46.832us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.330s	15.878us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.250s	52.767us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.900s	39.275us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.960s	97.728us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.330s	15.878us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	39.275us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	16.710s	76.679us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.570s	470.099us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.530s	12.662us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.050s	478.680us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	35.040s	3.762ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_prog_failure	8.050s	478.680us	50	50	100.00
		lc_ctrl_errors	35.040s	3.762ms	50	50	100.00
		lc_ctrl_security_escalation	21.830s	724.543us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.868m	10.953ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.830s	2.319ms	20	20	100.00
		lc_ctrl_jtag_errors	1.944m	3.160ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.180s	1.402ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.670s	791.246us	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.830s	2.319ms	20	20	100.00
		lc_ctrl_jtag_errors	1.944m	3.160ms	20	20	100.00
		lc_ctrl_jtag_access	20.590s	613.905us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.620s	1.949ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.260s	191.165us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.160s	585.415us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.510s	3.707ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.920s	2.240ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.050s	139.359us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.290s	1.254ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.000s	153.900us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.430s	5.792ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.610s	14.214us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.004m	40.192ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.280s	34.334us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.790s	173.285us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.790s	173.285us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.420s	46.832us	5	5	100.00
		lc_ctrl_csr_rw	1.330s	15.878us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	39.275us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.690s	480.251us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.420s	46.832us	5	5	100.00
		lc_ctrl_csr_rw	1.330s	15.878us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	39.275us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.690s	480.251us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
		lc_ctrl_tl_intg_err	4.150s	1.837ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.150s	1.837ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.570s	470.099us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	59.100s	291.329us	50	50	100.00
		lc_ctrl_sec_cm	1.012m	876.106us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.830s	724.543us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	16.710s	76.679us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.670s	791.246us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	34.120s	782.041us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	34.120s	782.041us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.850s	2.610ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.500s	525.746us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.500s	525.746us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.469m	25.547ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.92	95.29	93.40	100.00	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.64196542296534819314072241456198713086748954571919850700188447676276023347140
      Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 203774955 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 203774955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.70250000522023432153410996853291115846270671346044228533991460906832780004883
      Line 6729, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7456729242 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7456729242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.28320010485212075504377429744345401083939430514902848105057149802648938681236
      Line 3097, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5580551185 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 5580551185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 43.lc_ctrl_stress_all_with_rand_reset.26685679673616158766980133947600181978371783639848323883927101002594277059530
      Line 4428, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7367824850 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 7367824850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.10_08.11.26
• 2024.09.05_04.20.58
• 2024.09.02_11.30.45
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