LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	15.730s	239.931us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.870s	76.121us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.720s	16.467us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	4.590s	355.058us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.920s	93.545us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	3.050s	54.875us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.720s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.920s	93.545us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.400s	1.395ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.430s	1.373ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.330s	58.612us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.170s	106.728us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.530s	633.361us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_prog_failure	7.170s	106.728us	50	50	100.00
		lc_ctrl_errors	21.530s	633.361us	50	50	100.00
		lc_ctrl_security_escalation	15.710s	360.621us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.772m	15.108ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.410s	3.832ms	20	20	100.00
		lc_ctrl_jtag_errors	1.591m	14.943ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.640s	3.360ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	44.550s	6.569ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.410s	3.832ms	20	20	100.00
		lc_ctrl_jtag_errors	1.591m	14.943ms	20	20	100.00
		lc_ctrl_jtag_access	26.860s	4.164ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.570s	1.477ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.830s	458.559us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.470s	104.784us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	1.069m	4.137ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.350s	1.234ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.550s	45.428us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.740s	202.762us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.540s	72.683us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.390s	442.547us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.690s	199.200us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	16.355m	34.992ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.810s	82.134us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	7.170s	171.019us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	7.170s	171.019us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.870s	76.121us	5	5	100.00
		lc_ctrl_csr_rw	1.720s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.920s	93.545us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.770s	43.667us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.870s	76.121us	5	5	100.00
		lc_ctrl_csr_rw	1.720s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.920s	93.545us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.770s	43.667us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
		lc_ctrl_tl_intg_err	10.160s	379.200us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	10.160s	379.200us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.430s	1.373ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	43.130s	1.221ms	50	50	100.00
		lc_ctrl_sec_cm	40.090s	1.122ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.710s	360.621us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.400s	1.395ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	44.550s	6.569ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.700s	733.458us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.700s	733.458us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.310s	14.321ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.320s	2.367ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.320s	2.367ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.375m	5.645ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.90	95.38	93.40	100.00	98.49	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.104904931900286848477346236249823359718546610104885396905099203408155256933583
      Line 2113, in log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14326367078 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14326367078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.lc_ctrl_stress_all_with_rand_reset.49986888123120956183227947254607630106005127985751893985832406831536787662323
      Line 142, in log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2755808604 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2755808604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.59236533536538493501343400598666913648353195984099908642301668316755397093527
      Line 6090, in log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2100536432 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2100536432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.10_10.15.18
• 2024.10.04_00.42.11
• 2024.09.25_11.01.11
• 2024.09.19_09.04.56
• 2024.09.12_10.16.35
• 2024.09.10_08.11.26
• 2024.09.05_04.20.58