LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.140s	196.083us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	61.241us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.040s	16.273us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.980s	405.457us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.900s	44.192us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.350s	135.651us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.040s	16.273us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	44.192us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.360s	64.259us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.170s	2.157ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	13.560us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.140s	122.048us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.360s	4.659ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_prog_failure	5.140s	122.048us	50	50	100.00
		lc_ctrl_errors	22.360s	4.659ms	50	50	100.00
		lc_ctrl_security_escalation	16.690s	486.702us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.369m	9.176ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.830s	3.993ms	20	20	100.00
		lc_ctrl_jtag_errors	1.648m	12.922ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.590s	2.018ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.570s	4.036ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.830s	3.993ms	20	20	100.00
		lc_ctrl_jtag_errors	1.648m	12.922ms	20	20	100.00
		lc_ctrl_jtag_access	20.410s	3.512ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.220s	5.207ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.070s	401.684us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.130s	168.172us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	18.430s	5.763ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.890s	717.446us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.920s	45.210us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.620s	343.716us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.000s	62.080us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.750s	637.735us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.460s	27.944us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.448m	61.831ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.490s	31.193us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.190s	2.301ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.190s	2.301ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	61.241us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	16.273us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	44.192us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	155.828us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	61.241us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	16.273us	20	20	100.00
		lc_ctrl_csr_aliasing	1.900s	44.192us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	155.828us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
		lc_ctrl_tl_intg_err	4.480s	1.394ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.480s	1.394ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.170s	2.157ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.980s	3.005ms	50	50	100.00
		lc_ctrl_sec_cm	41.300s	228.894us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.690s	486.702us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.360s	64.259us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.570s	4.036ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.720s	732.292us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.720s	732.292us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.400s	726.169us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.120s	2.473ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.120s	2.473ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.609m	41.596ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.89	95.77	93.31	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.33910994537077154957014172979083154450973182036148458735418341228623209793199
      Line 1681, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24395418823 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24395418823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.48545700537408384612652803450835914124478449341971479292716145436115702880438
      Line 21113, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25317513218 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25317513218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.21035851824324270880923409531449821045129095819289290892628488946571712419418
      Line 10864, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54093366865 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 54093366865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.lc_ctrl_stress_all_with_rand_reset.68701610201116531518089440417455272786540941973996855076674573605053282690352
      Line 22040, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55675481771 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 55675481771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.96396593888883052638766209177085012935721988851238696352799112502261397398826
      Line 24187, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82345037858 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 82345037858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.50455796851583671095238522121141402002773389362763546175046851301742130309480
      Line 36287, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.53719014251014041426279103804000524621269762453684965996487958570761912835934
      Line 8800, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9376054801 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 9376054801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.05.03_05.12.51
• 2024.05.01_04.24.15
• 2024.04.29_08.00.40
• 2024.04.26_07.50.13
• 2024.04.24_08.01.52
• 2024.04.22_07.25.13