LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.600s	538.915us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.800s	16.172us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.730s	30.898us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.640s	81.643us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.190s	61.649us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.770s	45.420us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.730s	30.898us	20	20	100.00
		lc_ctrl_csr_aliasing	2.190s	61.649us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.580s	386.088us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	28.730s	725.977us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.450s	22.709us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.010s	528.550us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.650s	685.471us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_prog_failure	6.010s	528.550us	50	50	100.00
		lc_ctrl_errors	28.650s	685.471us	50	50	100.00
		lc_ctrl_security_escalation	18.520s	404.525us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.649m	3.197ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.920s	1.812ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	9.644ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.140s	419.789us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	45.360s	5.199ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.920s	1.812ms	20	20	100.00
		lc_ctrl_jtag_errors	2.092m	9.644ms	20	20	100.00
		lc_ctrl_jtag_access	19.890s	12.222ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.040s	1.349ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	7.320s	717.032us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.460s	111.582us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	37.850s	1.102ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.710s	4.142ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.860s	39.511us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.180s	1.239ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.160s	1.128ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	30.220s	9.694ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.720s	14.609us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.923m	43.668ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.140s	28.099us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	7.520s	618.363us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	7.520s	618.363us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.800s	16.172us	5	5	100.00
		lc_ctrl_csr_rw	1.730s	30.898us	20	20	100.00
		lc_ctrl_csr_aliasing	2.190s	61.649us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.680s	93.742us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.800s	16.172us	5	5	100.00
		lc_ctrl_csr_rw	1.730s	30.898us	20	20	100.00
		lc_ctrl_csr_aliasing	2.190s	61.649us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.680s	93.742us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
		lc_ctrl_tl_intg_err	8.500s	177.162us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	8.500s	177.162us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	28.730s	725.977us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.200s	522.154us	50	50	100.00
		lc_ctrl_sec_cm	39.700s	273.849us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.520s	404.525us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.580s	386.088us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	45.360s	5.199ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.460s	704.575us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.460s	704.575us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	34.650s	12.293ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.480s	610.516us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.480s	610.516us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.909m	22.257ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.60	97.97	95.68	93.40	95.35	98.53	99.00	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 29 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.7447408562702347033232914868558407340466487683740431275094456914836864170204
    Line 6819, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2701329087 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2701329087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.12602232073635475289030173991838762276740470903380538270735686516162538522537
    Line 5496, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38196953133 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38196953133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 26.lc_ctrl_stress_all_with_rand_reset.2210747407061062586250774198436243417614783630777630625462787683912673954390
    Line 2783, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23058546429 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 23058546429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.lc_ctrl_stress_all_with_rand_reset.71005532103986313873830202947612400901526879188251458935532132312336928285930
    Line 11102, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10201454152 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 10201454152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProd has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.lc_ctrl_stress_all_with_rand_reset.45470629481840530467639142928862167000349287370229619493112663438981013292610
    Line 2536, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 144365047 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStProd
  UVM_INFO @ 144365047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.91005613684745347212416092213653365213932272609347858689201997545899428998583
    Line 2350, in log /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1646298490 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked2
  UVM_INFO @ 1646298490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1cb1c3d135`