LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.610s	104.249us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.580s	55.330us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.420s	64.923us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.240s	68.332us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.860s	23.598us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.610s	30.728us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.420s	64.923us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	23.598us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.820s	397.561us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	30.000s	397.824us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.560s	13.954us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.660s	483.134us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	29.740s	558.845us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_prog_failure	6.660s	483.134us	50	50	100.00
		lc_ctrl_errors	29.740s	558.845us	50	50	100.00
		lc_ctrl_security_escalation	21.100s	607.952us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.464m	7.932ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.625ms	20	20	100.00
		lc_ctrl_jtag_errors	2.109m	32.653ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.260s	1.596ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	43.100s	1.203ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.625ms	20	20	100.00
		lc_ctrl_jtag_errors	2.109m	32.653ms	20	20	100.00
		lc_ctrl_jtag_access	27.180s	1.795ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	48.540s	4.617ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.050s	261.906us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.320s	213.532us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.820s	9.470ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.480s	1.450ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.270s	148.100us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.140s	1.241ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.540s	91.727us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.970s	509.969us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.610s	22.507us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.062m	194.896ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.800s	75.022us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.440s	323.300us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.440s	323.300us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.580s	55.330us	5	5	100.00
		lc_ctrl_csr_rw	1.420s	64.923us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	23.598us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.190s	171.424us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.580s	55.330us	5	5	100.00
		lc_ctrl_csr_rw	1.420s	64.923us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	23.598us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.190s	171.424us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
		lc_ctrl_tl_intg_err	4.390s	114.791us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.390s	114.791us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	30.000s	397.824us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	44.670s	264.808us	50	50	100.00
		lc_ctrl_sec_cm	46.060s	822.455us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.100s	607.952us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.820s	397.561us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	43.100s	1.203ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.880s	1.493ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.880s	1.493ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.320s	3.187ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.250s	807.698us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.250s	807.698us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.354m	7.062ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.97	96.04	93.40	100.00	98.53	99.00	95.94

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.91341419120470458789568105810301332739475882244323384194095588173637715918163
    Line 791, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4076110180 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4076110180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.6717439604400182477052709312766739786637019730379902985799604733301526053300
    Line 9782, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30766158447 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30766158447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.lc_ctrl_stress_all_with_rand_reset.113075402261855671366075927012755916650370921848417961980921314631323617502940
    Line 2450, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3506815838 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 3506815838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.lc_ctrl_stress_all_with_rand_reset.5006755555275871247442085144096418897344081561515196964536145650340284779280
    Line 9350, in log /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9256302695 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 9256302695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`