LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.870s	149.268us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.760s	56.470us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.600s	16.823us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.650s	188.946us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.000s	41.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.670s	81.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.600s	16.823us	20	20	100.00
		lc_ctrl_csr_aliasing	2.000s	41.635us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.590s	141.887us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.480s	1.659ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.380s	10.997us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.530s	452.728us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.700s	865.684us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_prog_failure	6.530s	452.728us	50	50	100.00
		lc_ctrl_errors	22.700s	865.684us	50	50	100.00
		lc_ctrl_security_escalation	17.780s	384.905us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.837m	7.270ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.770s	638.413us	20	20	100.00
		lc_ctrl_jtag_errors	1.087m	2.480ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.640s	2.106ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.430s	895.085us	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.770s	638.413us	20	20	100.00
		lc_ctrl_jtag_errors	1.087m	2.480ms	20	20	100.00
		lc_ctrl_jtag_access	28.210s	4.161ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.330s	6.403ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.110s	151.820us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.710s	343.676us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.240s	1.802ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.770s	4.925ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	38.400us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.930s	539.214us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.570s	123.843us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	39.460s	2.845ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.930s	22.079us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.777m	23.581ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.810s	62.738us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.340s	122.687us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.340s	122.687us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.760s	56.470us	5	5	100.00
		lc_ctrl_csr_rw	1.600s	16.823us	20	20	100.00
		lc_ctrl_csr_aliasing	2.000s	41.635us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	203.457us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.760s	56.470us	5	5	100.00
		lc_ctrl_csr_rw	1.600s	16.823us	20	20	100.00
		lc_ctrl_csr_aliasing	2.000s	41.635us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	203.457us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
		lc_ctrl_tl_intg_err	3.990s	396.943us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.990s	396.943us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.480s	1.659ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.870s	1.357ms	50	50	100.00
		lc_ctrl_sec_cm	38.110s	775.009us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.780s	384.905us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.590s	141.887us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.430s	895.085us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.620s	5.405ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.620s	5.405ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	32.610s	667.263us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.060s	2.319ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.060s	2.319ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.250m	25.167ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1009	1030	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.33	97.97	95.95	93.40	100.00	98.53	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.76347268628480223440363490097749763861441857142661806458572106370922175864005
      Line 1587, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6206887756 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6206887756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.115135233869190437025169299007788227829107751106653918776060103497504107526450
      Line 4152, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9846329726 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9846329726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• Job timed out after * minutes has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.103568226054174167420982591586920651244206803852510058835591208821431790663254
      Log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 29.lc_ctrl_stress_all.100550500012899668759441799729778345540222424235150997429751773273352083928548
      Line 6520, in log /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 30011459123 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 30011459123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.04_00.42.24
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• 2024.09.19_09.05.09
• 2024.09.12_10.16.47
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