LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.420s	103.062us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.850s	39.800us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.530s	23.835us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.710s	65.939us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.680s	39.080us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.710s	183.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.530s	23.835us	20	20	100.00
		lc_ctrl_csr_aliasing	2.680s	39.080us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	17.910s	301.694us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.950s	684.040us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.360s	87.212us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.360s	151.325us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.950s	705.612us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_prog_failure	7.360s	151.325us	50	50	100.00
		lc_ctrl_errors	24.950s	705.612us	50	50	100.00
		lc_ctrl_security_escalation	15.060s	3.312ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.855m	11.379ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.876ms	20	20	100.00
		lc_ctrl_jtag_errors	1.370m	31.894ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.060s	1.702ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.510s	669.057us	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.876ms	20	20	100.00
		lc_ctrl_jtag_errors	1.370m	31.894ms	20	20	100.00
		lc_ctrl_jtag_access	31.080s	9.658ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	27.020s	4.377ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	7.400s	668.307us	10	10	100.00
		lc_ctrl_jtag_csr_rw	5.590s	139.828us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.640s	4.135ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	33.520s	4.575ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.870s	91.107us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.280s	866.306us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.860s	246.694us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	41.430s	14.126ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.790s	34.346us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.318m	87.628ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.910s	91.874us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	8.810s	199.995us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	8.810s	199.995us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.850s	39.800us	5	5	100.00
		lc_ctrl_csr_rw	1.530s	23.835us	20	20	100.00
		lc_ctrl_csr_aliasing	2.680s	39.080us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.590s	146.534us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.850s	39.800us	5	5	100.00
		lc_ctrl_csr_rw	1.530s	23.835us	20	20	100.00
		lc_ctrl_csr_aliasing	2.680s	39.080us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.590s	146.534us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
		lc_ctrl_tl_intg_err	6.710s	170.287us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.710s	170.287us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.950s	684.040us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	52.170s	1.720ms	50	50	100.00
		lc_ctrl_sec_cm	57.350s	469.822us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.060s	3.312ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	17.910s	301.694us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.510s	669.057us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.410s	3.875ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.410s	3.875ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.270s	3.467ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.300s	634.132us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.300s	634.132us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.618m	18.986ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	97.99	96.22	93.40	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.33790984214019429203868393157661452582429192170219654586748116459932649315092
      Line 809, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11803105947 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11803105947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.34744129779626299168797685044411546694560719222497271361984603241435666476145
      Line 3883, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2348679495 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2348679495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.89072533070351099901153007796496748216518616643467698336480413225480968583945
      Line 13048, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4781686320 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked7
        UVM_INFO @ 4781686320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.lc_ctrl_stress_all_with_rand_reset.55463910712260603787545085100029936412882857961367546771741757321150159612471
      Line 3575, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6299443134 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 6299443134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 2.lc_ctrl_stress_all.5174792179192540989740972700824207238409568295361766960662280913748543811330
      Line 4572, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 850314257 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 850314257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.108683222260873211715577561196760195840485188855499601041657129130863869331657
      Line 6202, in log /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1912894771 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1912894771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.10_08.11.38
• 2024.09.05_04.21.10
• 2024.09.02_11.30.57
• 2024.08.29_23.13.01
• 2024.08.28_06.56.32
• 2024.08.26_02.17.54
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