LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.630s	314.085us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.530s	59.610us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.690s	20.318us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.020s	356.422us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.370s	39.660us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.870s	28.571us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.690s	20.318us	20	20	100.00
		lc_ctrl_csr_aliasing	2.370s	39.660us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	18.680s	72.951us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.170s	431.731us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.390s	35.817us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.380s	102.758us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.630s	2.278ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_prog_failure	6.380s	102.758us	50	50	100.00
		lc_ctrl_errors	26.630s	2.278ms	50	50	100.00
		lc_ctrl_security_escalation	21.310s	1.316ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.993m	13.398ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.440s	979.330us	20	20	100.00
		lc_ctrl_jtag_errors	1.815m	7.236ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.230s	655.577us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	41.760s	8.219ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.440s	979.330us	20	20	100.00
		lc_ctrl_jtag_errors	1.815m	7.236ms	20	20	100.00
		lc_ctrl_jtag_access	29.880s	1.362ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.880s	4.793ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.610s	107.921us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.520s	922.095us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.540s	3.450ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.640s	5.869ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	50.280us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.280s	151.231us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.870s	211.640us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.750s	770.081us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	2.080s	45.141us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.357m	19.126ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.050s	110.175us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.280s	154.437us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.280s	154.437us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.530s	59.610us	5	5	100.00
		lc_ctrl_csr_rw	1.690s	20.318us	20	20	100.00
		lc_ctrl_csr_aliasing	2.370s	39.660us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.230s	42.504us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.530s	59.610us	5	5	100.00
		lc_ctrl_csr_rw	1.690s	20.318us	20	20	100.00
		lc_ctrl_csr_aliasing	2.370s	39.660us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.230s	42.504us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
		lc_ctrl_tl_intg_err	7.210s	1.170ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	7.210s	1.170ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.170s	431.731us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	49.000s	3.443ms	50	50	100.00
		lc_ctrl_sec_cm	49.960s	218.861us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.310s	1.316ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	18.680s	72.951us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	41.760s	8.219ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.180s	962.444us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.180s	962.444us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.430s	4.517ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.710s	1.281ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.710s	1.281ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.277m	36.996ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 27 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.64493451405095045126215852001966518451841092876378636231513153526771400786509
    Line 2896, in log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6820935361 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6820935361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.3768099881301575297426243651425697070731488767282984438252182027056471549969
    Line 997, in log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1432520277 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1432520277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.

Job returned non-zero exit code has 1 failures:

Test lc_ctrl has 1 failures.

cov_report
Log /workspaces/repo/scratch/os_regression_2024_10_11/lc_ctrl_volatile_unlock_enabled-sim-vcs/cov_report/cov_report.log

              Inclusivity and Diversity" (Refer to article 000036315 at
                          https://solvnetplus.synopsys.com)
  
  Error-[URG-NLCW] No license key
    URG failed to get a license key. Number of attempts to get a license key
    exceeded the limit (500).
    Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
    file.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:241: cov_report] Error 1