LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.280s	143.665us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.670s	68.777us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.540s	35.645us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.530s	26.572us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.270s	244.142us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.820s	176.542us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.540s	35.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.270s	244.142us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.430s	101.762us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.130s	295.294us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.380s	13.803us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.050s	126.948us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	32.330s	3.383ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_prog_failure	7.050s	126.948us	50	50	100.00
		lc_ctrl_errors	32.330s	3.383ms	49	50	98.00
		lc_ctrl_security_escalation	20.400s	3.333ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.891m	27.396ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.370s	734.725us	20	20	100.00
		lc_ctrl_jtag_errors	2.200m	4.779ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	22.440s	1.337ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.450s	1.985ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.370s	734.725us	20	20	100.00
		lc_ctrl_jtag_errors	2.200m	4.779ms	20	20	100.00
		lc_ctrl_jtag_access	35.140s	1.817ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.490s	4.718ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.580s	231.431us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.350s	224.262us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.560s	12.886ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.820s	868.707us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.210s	82.366us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.890s	127.380us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.840s	207.372us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	56.630s	6.528ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.670s	18.304us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.332m	114.123ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.060s	135.356us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.250s	117.952us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.250s	117.952us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.670s	68.777us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	35.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.270s	244.142us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.480s	49.857us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.670s	68.777us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	35.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.270s	244.142us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.480s	49.857us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.320s	798.296us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.320s	798.296us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.130s	295.294us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	44.430s	1.355ms	50	50	100.00
		lc_ctrl_sec_cm	49.700s	2.097ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.400s	3.333ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.430s	101.762us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.450s	1.985ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.400s	523.490us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.400s	523.490us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.480s	3.011ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	30.610s	5.240ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	30.610s	5.240ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.680m	20.500ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.97	95.59	93.40	100.00	98.53	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.16272771748420391709784911466510399707982839124282916954252517914136645687515
      Line 201, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 452686615 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 452686615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.89188650796055525505230627014819820882283230724972966409207645751580833011313
      Line 4115, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2384831042 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2384831042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 4.lc_ctrl_errors.52320915287813941831905103011629965979105682615268611515696251460261628125447
      Line 2058, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 422716852 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 422716852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 21.lc_ctrl_stress_all.49234226561312254379266381232061871896589317459200816088283502649703729529469
      Line 7567, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 30117304931 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 30117304931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.45201274562865042771129214759293425008935892311559098759171786097718258250225
      Line 6720, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2377607680 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2377607680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRaw has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.49730255934884503394347430633256341167778058200008038737612457763347626129333
      Line 4185, in log /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2400476250 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStRaw
        UVM_INFO @ 2400476250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.19_09.05.09
• 2024.09.12_10.16.47
• 2024.09.10_08.11.38
• 2024.09.05_04.21.10
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