OTBN Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 38.659us 1 1 100.00
V1 single_binary otbn_single 1.117m 316.057us 96 100 96.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 16.169us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 31.235us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 35.171us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 63.041us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 101.360us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 31.235us 20 20 100.00
otbn_csr_aliasing 6.000s 63.041us 5 5 100.00
V1 mem_walk otbn_mem_walk 36.000s 4.731ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 18.000s 311.106us 5 5 100.00
V1 TOTAL 162 166 97.59
V2 reset_recovery otbn_reset 46.000s 599.737us 8 10 80.00
V2 multi_error otbn_multi_err 56.000s 230.825us 1 1 100.00
V2 back_to_back otbn_multi 1.050m 168.545us 6 10 60.00
V2 stress_all otbn_stress_all 1.850m 460.760us 10 10 100.00
V2 lc_escalation otbn_escalate 22.000s 78.670us 44 60 73.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 84.761us 5 5 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 39.000s 140.262us 10 10 100.00
V2 alert_test otbn_alert_test 9.000s 28.966us 50 50 100.00
V2 intr_test otbn_intr_test 6.000s 23.108us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 10.000s 1.130ms 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 10.000s 1.130ms 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 16.169us 5 5 100.00
otbn_csr_rw 7.000s 31.235us 20 20 100.00
otbn_csr_aliasing 6.000s 63.041us 5 5 100.00
otbn_same_csr_outstanding 7.000s 34.074us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 16.169us 5 5 100.00
otbn_csr_rw 7.000s 31.235us 20 20 100.00
otbn_csr_aliasing 6.000s 63.041us 5 5 100.00
otbn_same_csr_outstanding 7.000s 34.074us 20 20 100.00
V2 TOTAL 224 246 91.06
V2S mem_integrity otbn_imem_err 10.000s 104.665us 8 10 80.00
otbn_dmem_err 18.000s 64.114us 14 15 93.33
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 41.158us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 91.074us 5 5 100.00
otbn_mac_bignum_acc_err 12.000s 80.259us 4 5 80.00
otbn_urnd_err 6.000s 56.757us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 33.874us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 17.074us 1 2 50.00
V2S tl_intg_err otbn_sec_cm 4.100m 1.398ms 3 5 60.00
otbn_tl_intg_err 34.000s 244.293us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 37.000s 230.996us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 38.659us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 18.000s 64.114us 14 15 93.33
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 104.665us 8 10 80.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 34.000s 244.293us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 22.000s 78.670us 44 60 73.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 104.665us 8 10 80.00
otbn_dmem_err 18.000s 64.114us 14 15 93.33
otbn_zero_state_err_urnd 10.000s 84.761us 5 5 100.00
otbn_illegal_mem_acc 6.000s 33.874us 4 5 80.00
otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 104.665us 8 10 80.00
otbn_dmem_err 18.000s 64.114us 14 15 93.33
otbn_zero_state_err_urnd 10.000s 84.761us 5 5 100.00
otbn_illegal_mem_acc 6.000s 33.874us 4 5 80.00
otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 22.000s 78.670us 44 60 73.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 104.665us 8 10 80.00
otbn_dmem_err 18.000s 64.114us 14 15 93.33
otbn_zero_state_err_urnd 10.000s 84.761us 5 5 100.00
otbn_illegal_mem_acc 6.000s 33.874us 4 5 80.00
otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 29.302us 11 12 91.67
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.000s 55.716us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 2.117m 702.363us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 2.117m 702.363us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 10.000s 157.150us 7 10 70.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 35.000s 91.772us 9 10 90.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 30.000s 10.037ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 30.000s 10.037ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 12.000s 25.874us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_write_mem_integrity otbn_multi 1.050m 168.545us 6 10 60.00
V2S sec_cm_ctrl_flow_count otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 17.000s 62.750us 4 5 80.00
V2S sec_cm_key_sideload otbn_single 1.117m 316.057us 96 100 96.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.100m 1.398ms 3 5 60.00
V2S TOTAL 137 153 89.54
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 7.100m 6.653ms 6 10 60.00
V3 TOTAL 6 10 60.00
TOTAL 529 575 92.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 8 72.73
V2S 19 19 8 42.11
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.75 99.53 94.55 99.64 90.99 92.89 97.44 91.52 99.16

Failure Buckets

Past Results