OTBN Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 70.759us 1 1 100.00
V1 single_binary otbn_single 1.000m 266.354us 95 100 95.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 65.415us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 51.997us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 10.000s 129.465us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 16.056us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 34.974us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 51.997us 20 20 100.00
otbn_csr_aliasing 6.000s 16.056us 5 5 100.00
V1 mem_walk otbn_mem_walk 33.000s 1.549ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 16.000s 892.950us 5 5 100.00
V1 TOTAL 161 166 96.99
V2 reset_recovery otbn_reset 1.083m 4.052ms 10 10 100.00
V2 multi_error otbn_multi_err 59.000s 241.228us 1 1 100.00
V2 back_to_back otbn_multi 1.900m 442.839us 9 10 90.00
V2 stress_all otbn_stress_all 1.117m 808.794us 9 10 90.00
V2 lc_escalation otbn_escalate 13.000s 49.436us 47 60 78.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 37.318us 3 5 60.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 18.000s 56.826us 10 10 100.00
V2 alert_test otbn_alert_test 8.000s 16.586us 50 50 100.00
V2 intr_test otbn_intr_test 8.000s 13.855us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 10.000s 2.122ms 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 10.000s 2.122ms 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 65.415us 5 5 100.00
otbn_csr_rw 7.000s 51.997us 20 20 100.00
otbn_csr_aliasing 6.000s 16.056us 5 5 100.00
otbn_same_csr_outstanding 7.000s 46.454us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 65.415us 5 5 100.00
otbn_csr_rw 7.000s 51.997us 20 20 100.00
otbn_csr_aliasing 6.000s 16.056us 5 5 100.00
otbn_same_csr_outstanding 7.000s 46.454us 20 20 100.00
V2 TOTAL 229 246 93.09
V2S mem_integrity otbn_imem_err 11.000s 201.670us 10 10 100.00
otbn_dmem_err 13.000s 17.873us 13 15 86.67
V2S internal_integrity otbn_alu_bignum_mod_err 14.000s 121.587us 5 5 100.00
otbn_controller_ispr_rdata_err 9.000s 36.603us 5 5 100.00
otbn_mac_bignum_acc_err 28.000s 797.977us 5 5 100.00
otbn_urnd_err 7.000s 8.501us 1 2 50.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 19.940us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 14.113us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 4.183m 4.612ms 3 5 60.00
otbn_tl_intg_err 32.000s 331.903us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 36.000s 201.908us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 70.759us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 13.000s 17.873us 13 15 86.67
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 201.670us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 32.000s 331.903us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 13.000s 49.436us 47 60 78.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 201.670us 10 10 100.00
otbn_dmem_err 13.000s 17.873us 13 15 86.67
otbn_zero_state_err_urnd 8.000s 37.318us 3 5 60.00
otbn_illegal_mem_acc 8.000s 19.940us 5 5 100.00
otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 201.670us 10 10 100.00
otbn_dmem_err 13.000s 17.873us 13 15 86.67
otbn_zero_state_err_urnd 8.000s 37.318us 3 5 60.00
otbn_illegal_mem_acc 8.000s 19.940us 5 5 100.00
otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 13.000s 49.436us 47 60 78.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 201.670us 10 10 100.00
otbn_dmem_err 13.000s 17.873us 13 15 86.67
otbn_zero_state_err_urnd 8.000s 37.318us 3 5 60.00
otbn_illegal_mem_acc 8.000s 19.940us 5 5 100.00
otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 20.569us 11 12 91.67
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 24.488us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 43.000s 129.793us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 43.000s 129.793us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 13.000s 430.243us 5 10 50.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 41.527us 9 10 90.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 2.083m 10.011ms 4 5 80.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 2.083m 10.011ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 11.000s 31.958us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_write_mem_integrity otbn_multi 1.900m 442.839us 9 10 90.00
V2S sec_cm_ctrl_flow_count otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 13.000s 139.054us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 1.000m 266.354us 95 100 95.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.183m 4.612ms 3 5 60.00
V2S TOTAL 140 153 91.50
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 31.267m 24.165ms 8 10 80.00
V3 TOTAL 8 10 80.00
TOTAL 538 575 93.57

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 7 63.64
V2S 19 19 12 63.16
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.74 99.52 94.33 99.62 90.97 93.01 94.87 91.52 99.16

Failure Buckets

Past Results