4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 0 | 1 | 0.00 | ||
| V1 | single_binary | otbn_single | 0 | 100 | 0.00 | ||
| V1 | csr_hw_reset | otbn_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | otbn_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | otbn_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | otbn_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 0 | 20 | 0.00 | ||
| otbn_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | otbn_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | otbn_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 166 | 0.00 | |||
| V2 | reset_recovery | otbn_reset | 0 | 10 | 0.00 | ||
| V2 | multi_error | otbn_multi_err | 0 | 1 | 0.00 | ||
| V2 | back_to_back | otbn_multi | 0 | 10 | 0.00 | ||
| V2 | stress_all | otbn_stress_all | 0 | 10 | 0.00 | ||
| V2 | lc_escalation | otbn_escalate | 0 | 60 | 0.00 | ||
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 0 | 5 | 0.00 | ||
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 0 | 10 | 0.00 | ||
| V2 | alert_test | otbn_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | otbn_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | otbn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 0 | 5 | 0.00 | ||
| otbn_csr_rw | 0 | 20 | 0.00 | ||||
| otbn_csr_aliasing | 0 | 5 | 0.00 | ||||
| otbn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 0 | 5 | 0.00 | ||
| otbn_csr_rw | 0 | 20 | 0.00 | ||||
| otbn_csr_aliasing | 0 | 5 | 0.00 | ||||
| otbn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 246 | 0.00 | |||
| V2S | mem_integrity | otbn_imem_err | 0 | 10 | 0.00 | ||
| otbn_dmem_err | 0 | 15 | 0.00 | ||||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 0 | 5 | 0.00 | ||
| otbn_controller_ispr_rdata_err | 0 | 5 | 0.00 | ||||
| otbn_mac_bignum_acc_err | 0 | 5 | 0.00 | ||||
| otbn_urnd_err | 0 | 2 | 0.00 | ||||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 0 | 5 | 0.00 | ||
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 0 | 2 | 0.00 | ||
| V2S | tl_intg_err | otbn_sec_cm | 0 | 5 | 0.00 | ||
| otbn_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | prim_fsm_check | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_count_check | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_scramble | otbn_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 0 | 15 | 0.00 | ||
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 0 | 10 | 0.00 | ||
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 0 | 60 | 0.00 | ||
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 0 | 10 | 0.00 | ||
| otbn_dmem_err | 0 | 15 | 0.00 | ||||
| otbn_zero_state_err_urnd | 0 | 5 | 0.00 | ||||
| otbn_illegal_mem_acc | 0 | 5 | 0.00 | ||||
| otbn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scramble_key_sideload | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 0 | 10 | 0.00 | ||
| otbn_dmem_err | 0 | 15 | 0.00 | ||||
| otbn_zero_state_err_urnd | 0 | 5 | 0.00 | ||||
| otbn_illegal_mem_acc | 0 | 5 | 0.00 | ||||
| otbn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 0 | 60 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 0 | 10 | 0.00 | ||
| otbn_dmem_err | 0 | 15 | 0.00 | ||||
| otbn_zero_state_err_urnd | 0 | 5 | 0.00 | ||||
| otbn_illegal_mem_acc | 0 | 5 | 0.00 | ||||
| otbn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 0 | 12 | 0.00 | ||
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 0 | 5 | 0.00 | ||
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 0 | 10 | 0.00 | ||
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 0 | 10 | 0.00 | ||
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 0 | 5 | 0.00 | ||
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 0 | 5 | 0.00 | ||
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 0 | 7 | 0.00 | ||
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_write_mem_integrity | otbn_multi | 0 | 10 | 0.00 | ||
| V2S | sec_cm_ctrl_flow_count | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 0 | 5 | 0.00 | ||
| V2S | sec_cm_key_sideload | otbn_single | 0 | 100 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 153 | 0.00 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 0 | 575 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 19 | 19 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 577 failures:
Test otbn_smoke has 1 failures.
Test otbn_single has 100 failures.
0.otbn_single.91944765692674317316402630584016982701110558911622507465905551911016593652214
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_single/latest/run.log
1.otbn_single.29967101924648082274450376052468376513998926971736796086447965269602542516418
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_single/latest/run.log
... and 98 more failures.
Test otbn_multi has 10 failures.
0.otbn_multi.101166015953768259559503359756157051439450193803857760608437295469446606712257
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi/latest/run.log
1.otbn_multi.59111610445663533981336836219943759771843066530996506345392832193326974923587
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_multi/latest/run.log
... and 8 more failures.
Test otbn_reset has 10 failures.
0.otbn_reset.26745733053872171347335565690739240408386012721467726594028441484991337458410
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_reset/latest/run.log
1.otbn_reset.53329837470529487793196698281923290896963045686731891227689375868504189094470
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_reset/latest/run.log
... and 8 more failures.
Test otbn_multi_err has 1 failures.
... and 36 more tests.
Test default has 1 failures.
Test cover_reg_top has 1 failures.