OTBN Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	37.907us	1	1	100.00
V1	single_binary	otbn_single	2.983m	846.192us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	18.482us	5	5	100.00
V1	csr_rw	otbn_csr_rw	20.000s	10.508us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	462.282us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	11.000s	48.991us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	55.270us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	20.000s	10.508us	20	20	100.00
		otbn_csr_aliasing	11.000s	48.991us	5	5	100.00
V1	mem_walk	otbn_mem_walk	51.000s	1.824ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	448.589us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	37.000s	92.820us	10	10	100.00
V2	multi_error	otbn_multi_err	11.000s	62.479us	0	1	0.00
V2	back_to_back	otbn_multi	10.283m	2.920ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.783m	1.927ms	10	10	100.00
V2	lc_escalation	otbn_escalate	35.000s	160.973us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	26.784us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	147.855us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	19.808us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	16.708us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	75.835us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	75.835us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	18.482us	5	5	100.00
		otbn_csr_rw	20.000s	10.508us	20	20	100.00
		otbn_csr_aliasing	11.000s	48.991us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	54.961us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	18.482us	5	5	100.00
		otbn_csr_rw	20.000s	10.508us	20	20	100.00
		otbn_csr_aliasing	11.000s	48.991us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	54.961us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	12.000s	31.734us	10	10	100.00
		otbn_dmem_err	17.000s	42.123us	14	15	93.33
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	68.847us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	130.839us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	39.914us	5	5	100.00
		otbn_urnd_err	11.000s	31.508us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	42.073us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	34.484us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
		otbn_tl_intg_err	38.000s	286.357us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	49.000s	290.897us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	37.907us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	42.123us	14	15	93.33
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	31.734us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	38.000s	286.357us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	35.000s	160.973us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	31.734us	10	10	100.00
		otbn_dmem_err	17.000s	42.123us	14	15	93.33
		otbn_zero_state_err_urnd	11.000s	26.784us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	42.073us	5	5	100.00
		otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	31.734us	10	10	100.00
		otbn_dmem_err	17.000s	42.123us	14	15	93.33
		otbn_zero_state_err_urnd	11.000s	26.784us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	42.073us	5	5	100.00
		otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	35.000s	160.973us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	31.734us	10	10	100.00
		otbn_dmem_err	17.000s	42.123us	14	15	93.33
		otbn_zero_state_err_urnd	11.000s	26.784us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	42.073us	5	5	100.00
		otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	34.732us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	24.581us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	47.000s	372.729us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	47.000s	372.729us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	115.220us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	60.051us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	51.000s	10.004ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	51.000s	10.004ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	18.190us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	10.283m	2.920ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	184.174us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.983m	846.192us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.300m	1.952ms	5	5	100.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.450m	11.155ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			554	575	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.51	94.11	99.60	93.51	93.56	97.44	91.15	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

3.otbn_escalate.78738637423433695286926265988349941452560699892522569001562371900709722636630
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 53462958 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 53462958 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  53462958 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  53462958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.72749656082932534006339771846239538086535943214628691041555580888395586955688
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 91986064 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 91986064 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  91986064 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  91986064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

8.otbn_escalate.92486422228634414021554536338082433120100420572667707413475003464503463261030
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16641085 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16641085 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16641085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.otbn_escalate.110626682798211174324420606020182877718643382350382497614470438015456519605304
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 55258175 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  55258175 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  55258175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 3.otbn_stress_all_with_rand_reset.39495776663231045869849251296548978175726073241708807027467759046179593668448
    Line 378, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1445308618 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1445308618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.13516829282497610502757621377156061115299334535444722484615540092677271167492
    Line 422, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2837750430 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2837750430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

6.otbn_stress_all_with_rand_reset.92733443692057321816329119675535222625980141237549582711718167438245519198502
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4114, which encodes to -2057, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_dmem_err has 1 failures.

7.otbn_dmem_err.10644959157641823673739905021818582092288188737519710250626129131132470412302
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_dmem_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4854, which encodes to -2427, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

31.otbn_escalate.60713273885143182740681533806156447238420834108734244832651437740715549794064
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  UVM_FATAL @  92276424 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  92276424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.54709395259711049739188033987214337538200640638167089617169892267464372995814
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  UVM_FATAL @  31342324 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  31342324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

35.otbn_escalate.91547258746015909537259838027600181107855929952178647915013081050494852609281
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log

  UVM_FATAL @  19592853 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  19592853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.106181988114970198733777117775651699320176565383891079092570474427704947025547
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  UVM_FATAL @   6216206 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   6216206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.47630550587869975376701797735056858569963788787556444361497643749519976960584
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 62478727 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  62478727 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  62478727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.80916912644458038518314041347168640880045373524759342925392384318884785795631
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10004269645 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10004269645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 53.otbn_escalate.33859292195179359694014486403667122497222408454864286373834441258297558401167
    Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1351861 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1351861 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1351861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```