OTBN Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	122.039us	1	1	100.00
V1	single_binary	otbn_single	58.000s	452.957us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	55.725us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	30.693us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	135.669us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	16.073us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	41.122us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	30.693us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.073us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	1.253ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	464.388us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	34.000s	131.368us	10	10	100.00
V2	multi_error	otbn_multi_err	9.000s	28.556us	0	1	0.00
V2	back_to_back	otbn_multi	2.417m	2.433ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.000m	591.766us	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	69.148us	45	60	75.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	18.770us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	198.769us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	34.993us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	15.392us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	219.765us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	219.765us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	55.725us	5	5	100.00
		otbn_csr_rw	9.000s	30.693us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.073us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	48.034us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	55.725us	5	5	100.00
		otbn_csr_rw	9.000s	30.693us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.073us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	48.034us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	14.000s	23.229us	10	10	100.00
		otbn_dmem_err	12.000s	30.540us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	29.000s	409.743us	5	5	100.00
		otbn_controller_ispr_rdata_err	9.000s	218.265us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	65.043us	5	5	100.00
		otbn_urnd_err	6.000s	25.673us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	31.500us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	36.304us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
		otbn_tl_intg_err	31.000s	221.024us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	226.771us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	122.039us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	30.540us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	23.229us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	221.024us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	69.148us	45	60	75.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	23.229us	10	10	100.00
		otbn_dmem_err	12.000s	30.540us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.500us	5	5	100.00
		otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	23.229us	10	10	100.00
		otbn_dmem_err	12.000s	30.540us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.500us	5	5	100.00
		otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	69.148us	45	60	75.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	23.229us	10	10	100.00
		otbn_dmem_err	12.000s	30.540us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	18.770us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	31.500us	5	5	100.00
		otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	33.577us	9	12	75.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	13.730us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	48.000s	1.406ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	48.000s	1.406ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	23.303us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	41.000s	172.407us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.433m	10.006ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.433m	10.006ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	21.000s	64.789us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.417m	2.433ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	45.015us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	58.000s	452.957us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.100m	9.711ms	5	5	100.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.750m	10.179ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.84	99.51	94.15	99.61	93.57	93.22	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

13.otbn_escalate.17567933530365263965847671968864704364512346254072379110184671714844212526716
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3240265 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3240265 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3240265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.otbn_escalate.107418106223641486492080970421170591533175149249336910160208415688189399873567
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 32210631 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32210631 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  32210631 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  32210631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 4 failures:

Test otbn_escalate has 4 failures.

22.otbn_escalate.68371074600203642080595837654853278730117795335794734544912710917059739521473
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  UVM_FATAL @   9799864 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9799864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.otbn_escalate.78931244746036335230830345114894033547442067508775411255368063261496345869339
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log

  UVM_FATAL @  15789809 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  15789809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 3 failures:
- Test otbn_escalate has 3 failures.
  - 18.otbn_escalate.111808448538414125397310962013869694302488654130537509250478771826475988845290
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
```
  UVM_FATAL @   3870237 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   3870237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.otbn_escalate.31145352089441381816358509669437405890722933133829415524441885917691125791404
    Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
```
  UVM_FATAL @   4906366 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   4906366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.104907153325211843464581083247314622963277057383913080883219845442687497919404
    Line 442, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3622247063 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3622247063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.8687027932647823061256316391027474130934709492245935392526277250887041940037
    Line 418, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10178581868 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10178581868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_ctrl_redun has 2 failures.

1.otbn_ctrl_redun.14347085891951729549529458739555308922300342459146821455465625499471486822296
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4141560 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4141560 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4141560 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   4141560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_ctrl_redun.52966887375377858784927674087860106367782436963242832543807671776504853630268
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12243418 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 12243418 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  12243418 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12243418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

33.otbn_escalate.90863790137947508607018919994301643294540819566331312312519929939554550539266
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7243467 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7243467 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   7243467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

58.otbn_escalate.80504305624118458924122317859023201745061946225637883798134402180997938799743
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1300340 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1300340 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1300340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.99362695604792197120211742075369065656407332490836391507140529647580377309080
    Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 28556243 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  28556243 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  28556243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 1.otbn_stack_addr_integ_chk.30733149314977370380192291856768092124517537711316990699811392798112689138571
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10005797703 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10005797703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

2.otbn_stress_all_with_rand_reset.54526437462443143202518387827398489109030077211376511507887378938415606143473
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6966, which encodes to -3483, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.96833211324232640988767244677202332958952826694240670536301370214022696650834
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10004207257 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10004207257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.53379429381930428622328776885524079397229320811682868400760807110571758178192
    Line 404, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1335783003 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1335783003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.26451533852900183117109786359731180409069897973416029004563944225897387270144
    Line 416, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_rnd_if.sv,175): (time 1420492532 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if.EdgePREFETCHINGToFULL_A has failed (2 cycles, starting 1420482532 PS)
  UVM_ERROR @ 1420492532 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
  UVM_INFO @ 1420492532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 11.otbn_ctrl_redun.110030660070148395631260490229926517298165696180872532262696975841642046141332
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @   8795468 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @   8795468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```