OTBN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 11.000s 132.289us 1 1 100.00
V1 single_binary otbn_single 29.000s 324.268us 100 100 100.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 20.281us 5 5 100.00
V1 csr_rw otbn_csr_rw 10.000s 40.457us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 11.000s 54.356us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 64.886us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 14.000s 36.226us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 10.000s 40.457us 20 20 100.00
otbn_csr_aliasing 6.000s 64.886us 5 5 100.00
V1 mem_walk otbn_mem_walk 51.000s 1.840ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 28.000s 437.451us 5 5 100.00
V1 TOTAL 166 166 100.00
V2 reset_recovery otbn_reset 41.000s 106.207us 10 10 100.00
V2 multi_error otbn_multi_err 15.000s 89.353us 0 1 0.00
V2 back_to_back otbn_multi 3.767m 972.682us 10 10 100.00
V2 stress_all otbn_stress_all 2.283m 577.265us 9 10 90.00
V2 lc_escalation otbn_escalate 1.117m 1.082ms 44 60 73.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 167.098us 5 5 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 25.000s 308.702us 9 10 90.00
V2 alert_test otbn_alert_test 11.000s 65.429us 50 50 100.00
V2 intr_test otbn_intr_test 11.000s 18.230us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 16.000s 137.342us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 16.000s 137.342us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 20.281us 5 5 100.00
otbn_csr_rw 10.000s 40.457us 20 20 100.00
otbn_csr_aliasing 6.000s 64.886us 5 5 100.00
otbn_same_csr_outstanding 11.000s 24.888us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 20.281us 5 5 100.00
otbn_csr_rw 10.000s 40.457us 20 20 100.00
otbn_csr_aliasing 6.000s 64.886us 5 5 100.00
otbn_same_csr_outstanding 11.000s 24.888us 20 20 100.00
V2 TOTAL 227 246 92.28
V2S mem_integrity otbn_imem_err 12.000s 74.804us 10 10 100.00
otbn_dmem_err 12.000s 34.794us 15 15 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 14.000s 74.336us 5 5 100.00
otbn_controller_ispr_rdata_err 10.000s 220.958us 5 5 100.00
otbn_mac_bignum_acc_err 13.000s 62.246us 4 5 80.00
otbn_urnd_err 10.000s 31.488us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 36.920us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 19.287us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 4.667m 4.804ms 5 5 100.00
otbn_tl_intg_err 23.000s 166.697us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 32.000s 1.390ms 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S prim_count_check otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_mem_scramble otbn_smoke 11.000s 132.289us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 12.000s 34.794us 15 15 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 12.000s 74.804us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 23.000s 166.697us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 1.117m 1.082ms 44 60 73.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 12.000s 74.804us 10 10 100.00
otbn_dmem_err 12.000s 34.794us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 167.098us 5 5 100.00
otbn_illegal_mem_acc 8.000s 36.920us 5 5 100.00
otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_scramble_key_sideload otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 12.000s 74.804us 10 10 100.00
otbn_dmem_err 12.000s 34.794us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 167.098us 5 5 100.00
otbn_illegal_mem_acc 8.000s 36.920us 5 5 100.00
otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 1.117m 1.082ms 44 60 73.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 12.000s 74.804us 10 10 100.00
otbn_dmem_err 12.000s 34.794us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 167.098us 5 5 100.00
otbn_illegal_mem_acc 8.000s 36.920us 5 5 100.00
otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 12.000s 39.999us 12 12 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 12.000s 69.217us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 45.000s 401.412us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 45.000s 401.412us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 835.105us 8 10 80.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 12.000s 210.785us 9 10 90.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 48.000s 10.014ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 48.000s 10.014ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 36.000s 155.889us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_write_mem_integrity otbn_multi 3.767m 972.682us 10 10 100.00
V2S sec_cm_ctrl_flow_count otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 21.000s 94.629us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 29.000s 324.268us 100 100 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.667m 4.804ms 5 5 100.00
V2S TOTAL 147 153 96.08
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 12.550m 31.732ms 9 10 90.00
V3 TOTAL 9 10 90.00
TOTAL 549 575 95.48

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 11 11 7 63.64
V2S 19 19 15 78.95
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.85 99.50 93.98 99.60 93.48 93.71 97.44 90.46 99.16

Failure Buckets

Past Results