OTBN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	132.289us	1	1	100.00
V1	single_binary	otbn_single	29.000s	324.268us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	20.281us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	40.457us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	54.356us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	64.886us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	14.000s	36.226us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	40.457us	20	20	100.00
		otbn_csr_aliasing	6.000s	64.886us	5	5	100.00
V1	mem_walk	otbn_mem_walk	51.000s	1.840ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	28.000s	437.451us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	41.000s	106.207us	10	10	100.00
V2	multi_error	otbn_multi_err	15.000s	89.353us	0	1	0.00
V2	back_to_back	otbn_multi	3.767m	972.682us	10	10	100.00
V2	stress_all	otbn_stress_all	2.283m	577.265us	9	10	90.00
V2	lc_escalation	otbn_escalate	1.117m	1.082ms	44	60	73.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	167.098us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	25.000s	308.702us	9	10	90.00
V2	alert_test	otbn_alert_test	11.000s	65.429us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	18.230us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	16.000s	137.342us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	16.000s	137.342us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	20.281us	5	5	100.00
		otbn_csr_rw	10.000s	40.457us	20	20	100.00
		otbn_csr_aliasing	6.000s	64.886us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	24.888us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	20.281us	5	5	100.00
		otbn_csr_rw	10.000s	40.457us	20	20	100.00
		otbn_csr_aliasing	6.000s	64.886us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	24.888us	20	20	100.00
V2		TOTAL			227	246	92.28
V2S	mem_integrity	otbn_imem_err	12.000s	74.804us	10	10	100.00
		otbn_dmem_err	12.000s	34.794us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	74.336us	5	5	100.00
		otbn_controller_ispr_rdata_err	10.000s	220.958us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	62.246us	4	5	80.00
		otbn_urnd_err	10.000s	31.488us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	36.920us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	19.287us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
		otbn_tl_intg_err	23.000s	166.697us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	32.000s	1.390ms	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	132.289us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	34.794us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	74.804us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	23.000s	166.697us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.117m	1.082ms	44	60	73.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	74.804us	10	10	100.00
		otbn_dmem_err	12.000s	34.794us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	167.098us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	36.920us	5	5	100.00
		otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	74.804us	10	10	100.00
		otbn_dmem_err	12.000s	34.794us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	167.098us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	36.920us	5	5	100.00
		otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.117m	1.082ms	44	60	73.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	74.804us	10	10	100.00
		otbn_dmem_err	12.000s	34.794us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	167.098us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	36.920us	5	5	100.00
		otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	39.999us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	69.217us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	45.000s	401.412us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	45.000s	401.412us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	835.105us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	210.785us	9	10	90.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	48.000s	10.014ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	48.000s	10.014ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	36.000s	155.889us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.767m	972.682us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	21.000s	94.629us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	29.000s	324.268us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.667m	4.804ms	5	5	100.00
V2S		TOTAL			147	153	96.08
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.550m	31.732ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	7	63.64
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.50	93.98	99.60	93.48	93.71	97.44	90.46	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 10 failures:

Test otbn_escalate has 10 failures.

1.otbn_escalate.24496805569291044407552128502714185962613727899606233423463108916523257636471
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 3536453 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3536453 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3536453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_escalate.45252814789074964955411582207847247844099526028048275057224781957058696642264
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6606004 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6606004 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6606004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_sw_errs_fatal_chk has 1 failures.

0.otbn_sw_errs_fatal_chk.108306516971448874741522666045473795618852371665337340135086660648230824780323
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -7154, which encodes to -3577, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_rf_bignum_intg_err has 1 failures.

3.otbn_rf_bignum_intg_err.99115454479456442131899619022073511536397793687241794100058816482365766531121
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_bignum_intg_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5718, which encodes to -2859, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all has 1 failures.

5.otbn_stress_all.88139271450840640329524581534894853199403150954398388026037709140472906001867
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5726, which encodes to -2863, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

10.otbn_escalate.90959201797205736201019249119564775976537402155942077070872904099971888665750
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  UVM_FATAL @  10580134 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10580134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otbn_escalate.96780585153806197406209428235475381579774201755966884844881881675807336698988
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  UVM_FATAL @  11179990 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11179990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 0.otbn_stack_addr_integ_chk.110003093485421915169278797602777205110028030822469393865988503866003724319261
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10013759481 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10013759481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stack_addr_integ_chk.59681768739466366592216785510097731504872196687225047992375216637286050047493
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10024556048 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10024556048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

39.otbn_escalate.24505896610985585575647132805823843218982569589116290324327484052311524842611
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 1082397588 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 1082397588 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 1082397588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.otbn_escalate.94873564526480816126980781120669395322364021405515915086307986437823428625388
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35967750 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35967750 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35967750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.92714267971420873079716472294040976017391387880887665411695512879905888584373
    Line 374, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 89352830 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  89352830 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  89352830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_mac_bignum_acc_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_mac_bignum_acc_err has 1 failures.
  - 2.otbn_mac_bignum_acc_err.77296767921693037326350483322746982281791182066214069184904135906279224592946
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_mac_bignum_acc_err/latest/run.log
```
  UVM_FATAL @  22297683 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_mac_bignum_acc_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  22297683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 3.otbn_rf_base_intg_err.71255665822773854839782717846622598223827857247923109840111473168107753012292
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 835104855 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
  UVM_INFO @ 835104855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.104876517694590615394985196968031622165657967033185769768256411576630945326988
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 219626491 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 219626491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.70579501788775845924694844076964523165839268245585131188959165921267308931134
    Line 525, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7653173538 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 7653173538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 38.otbn_escalate.56626618219334991228607231740407941985875588991342463828304195438012128029241
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2135525 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2135525 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2135525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```