OTBN Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	129.192us	1	1	100.00
V1	single_binary	otbn_single	3.817m	1.934ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	15.510us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	16.646us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	107.725us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	29.386us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	119.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	16.646us	20	20	100.00
		otbn_csr_aliasing	9.000s	29.386us	5	5	100.00
V1	mem_walk	otbn_mem_walk	43.000s	374.170us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	31.000s	8.492ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	32.000s	356.114us	10	10	100.00
V2	multi_error	otbn_multi_err	6.000s	7.112us	0	1	0.00
V2	back_to_back	otbn_multi	5.000m	9.326ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.850m	474.149us	10	10	100.00
V2	lc_escalation	otbn_escalate	25.000s	55.872us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	21.155us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.783m	851.386us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	18.413us	50	50	100.00
V2	intr_test	otbn_intr_test	17.000s	15.260us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	481.150us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	481.150us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	15.510us	5	5	100.00
		otbn_csr_rw	10.000s	16.646us	20	20	100.00
		otbn_csr_aliasing	9.000s	29.386us	5	5	100.00
		otbn_same_csr_outstanding	17.000s	25.075us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	15.510us	5	5	100.00
		otbn_csr_rw	10.000s	16.646us	20	20	100.00
		otbn_csr_aliasing	9.000s	29.386us	5	5	100.00
		otbn_same_csr_outstanding	17.000s	25.075us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	13.000s	18.463us	10	10	100.00
		otbn_dmem_err	23.000s	701.164us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	99.426us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	57.418us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	666.720us	5	5	100.00
		otbn_urnd_err	6.000s	17.428us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	34.429us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	26.910us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	2.550m	665.210us	5	5	100.00
		otbn_tl_intg_err	23.000s	677.125us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	48.000s	259.363us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	129.192us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	23.000s	701.164us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	18.463us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	23.000s	677.125us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	55.872us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	18.463us	10	10	100.00
		otbn_dmem_err	23.000s	701.164us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.155us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	34.429us	5	5	100.00
		otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	18.463us	10	10	100.00
		otbn_dmem_err	23.000s	701.164us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.155us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	34.429us	5	5	100.00
		otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	55.872us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	18.463us	10	10	100.00
		otbn_dmem_err	23.000s	701.164us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	21.155us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	34.429us	5	5	100.00
		otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	17.709us	9	12	75.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	14.000s	51.472us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	30.000s	148.359us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	30.000s	148.359us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	1.477ms	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	59.000s	308.636us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	49.000s	10.045ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	49.000s	10.045ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	40.884us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	5.000m	9.326ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	26.000s	929.047us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.817m	1.934ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.550m	665.210us	5	5	100.00
V2S		TOTAL			146	153	95.42
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.783m	2.597ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			550	575	95.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	7	63.64
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.51	94.11	99.60	93.60	93.70	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

6.otbn_escalate.62414565608151880149734334178780627372605351556047517522217111754816360150370
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 35317242 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35317242 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35317242 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  35317242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.29956608654235322257220974809178849028874423746223737407062878041038573098125
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6548227 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6548227 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6548227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

1.otbn_zero_state_err_urnd.34429930911732802958843060243862172415361303354959623465290461722257692134339
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6954110 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   6954110 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6954110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

5.otbn_escalate.2596137131494567678239605081798846956420758874660450461895612243550603017552
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36405043 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  36405043 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  36405043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

10.otbn_ctrl_redun.108926565437034707432046228654392716626216413984021786775301061020688323149129
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4268046 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4268046 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4268046 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   4268046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 1.otbn_stack_addr_integ_chk.67649645326167697376067565791480825369290274445921023847099393242849355929102
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10044977558 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10044977558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stack_addr_integ_chk.40751648270759483232233545741019261418695926580076234532993891649801619123577
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10015227000 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10015227000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 2 failures:

Test otbn_ctrl_redun has 2 failures.

8.otbn_ctrl_redun.15198574557548831274783867001070196766429564254965519677120295688164079388384
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @   6623005 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @   6623005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_ctrl_redun.19804384216181790125101188404351073604421186886848298358494759317942892694622
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log

  UVM_FATAL @  35775103 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  35775103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_multi has 1 failures.

9.otbn_multi.109450910326235926387216315319951323136036124082848955650504254276075812696197
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4298, which encodes to -2149, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

81.otbn_single.70625412985998601139440524942151476208924274158266918443941280289307070516091
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/81.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4942, which encodes to -2471, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

9.otbn_escalate.10945787438032701658371332477364153131964989647334970543525557343918240305502
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3439354 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3439354 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3439354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.otbn_escalate.22048884234744705989370253736477910541249365686665542750672928554663571305176
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2503971 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2503971 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2503971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.27768551425635213020846086302004278120767114101474897511842365054468695557008
    Line 369, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 7111682 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @   7111682 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @   7111682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:754) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.101634640989959728041355545093731235778856527016359675217926237799301507140763
    Line 331, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 353855315 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 353855315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.63105669941832176977378206185081729981889174186359108378576139539487255484743
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 1477043030 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 1477043030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 9.otbn_rf_base_intg_err.77919739712617840699952089022407727018544574904080927850186149958577039153725
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 3393773346 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
  UVM_INFO @ 3393773346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 25.otbn_escalate.55158410369435990457760716323949929869672171881521897809440258662100081107955
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
```
  UVM_FATAL @   3473629 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   3473629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 31.otbn_escalate.19238921897122675979975870926311689401525931235065411645056455186307778658591
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log
```
  UVM_FATAL @  15373714 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  15373714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```