OTBN Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	464.021us	1	1	100.00
V1	single_binary	otbn_single	1.833m	465.620us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	12.000s	105.269us	5	5	100.00
V1	csr_rw	otbn_csr_rw	16.000s	42.548us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	19.000s	339.931us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	10.000s	40.146us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	22.000s	42.048us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	16.000s	42.548us	20	20	100.00
		otbn_csr_aliasing	10.000s	40.146us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.017m	6.353ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	215.519us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	45.000s	234.672us	10	10	100.00
V2	multi_error	otbn_multi_err	21.000s	101.701us	0	1	0.00
V2	back_to_back	otbn_multi	1.450m	724.635us	10	10	100.00
V2	stress_all	otbn_stress_all	3.267m	735.337us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	68.715us	44	60	73.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	38.373us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	25.040us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	32.023us	50	50	100.00
V2	intr_test	otbn_intr_test	14.000s	27.436us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	19.000s	381.545us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	19.000s	381.545us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	12.000s	105.269us	5	5	100.00
		otbn_csr_rw	16.000s	42.548us	20	20	100.00
		otbn_csr_aliasing	10.000s	40.146us	5	5	100.00
		otbn_same_csr_outstanding	22.000s	45.125us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	12.000s	105.269us	5	5	100.00
		otbn_csr_rw	16.000s	42.548us	20	20	100.00
		otbn_csr_aliasing	10.000s	40.146us	5	5	100.00
		otbn_same_csr_outstanding	22.000s	45.125us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	10.000s	23.047us	9	10	90.00
		otbn_dmem_err	13.000s	33.216us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	59.812us	5	5	100.00
		otbn_controller_ispr_rdata_err	52.000s	242.267us	5	5	100.00
		otbn_mac_bignum_acc_err	10.000s	20.662us	5	5	100.00
		otbn_urnd_err	9.000s	21.744us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	17.758us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	22.967us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
		otbn_tl_intg_err	30.000s	193.797us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	48.000s	260.339us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	464.021us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	33.216us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	23.047us	9	10	90.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	193.797us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	68.715us	44	60	73.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	23.047us	9	10	90.00
		otbn_dmem_err	13.000s	33.216us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	38.373us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	17.758us	5	5	100.00
		otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	23.047us	9	10	90.00
		otbn_dmem_err	13.000s	33.216us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	38.373us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	17.758us	5	5	100.00
		otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	68.715us	44	60	73.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	23.047us	9	10	90.00
		otbn_dmem_err	13.000s	33.216us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	38.373us	4	5	80.00
		otbn_illegal_mem_acc	8.000s	17.758us	5	5	100.00
		otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	23.144us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	75.001us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	53.000s	834.233us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	53.000s	834.233us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	37.968us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	39.000s	388.411us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	55.000s	10.057ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	55.000s	10.057ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	36.209us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.450m	724.635us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	167.894us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.833m	465.620us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.067m	3.018ms	5	5	100.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	42.567m	46.670ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			548	575	95.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	8	72.73
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.83	99.51	94.11	99.61	93.51	93.30	97.44	91.17	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 8 failures:

Test otbn_zero_state_err_urnd has 1 failures.

4.otbn_zero_state_err_urnd.81119706074937212104514539046171137648278712294859361564721120367152719144236
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6164174 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   6164174 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6164174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 6 failures.

10.otbn_escalate.43339212215051738040917636391482786844725470570016364132252435206661073783641
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29065093 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  29065093 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29065093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.otbn_escalate.2837142835808578937185082657593405133518445887295277045789884510411929037547
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 68714779 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  68714779 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  68714779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test otbn_ctrl_redun has 1 failures.

11.otbn_ctrl_redun.62232744993703293902112741705820789912673618745959818710997571871686380776579
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15272055 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 15272055 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  15272055 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15272055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

8.otbn_escalate.109225007531987565964135348487965798934502450343840025554938217546605174636750
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 15631602 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  15631602 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  15631602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.7044749338418244837485137252571273352327479798742601930964397621534737760809
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 12334600 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  12334600 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  12334600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

25.otbn_escalate.36297516864908555619214602321409202800355034092778724016258131675572947331067
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3659403 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3659403 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3659403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.otbn_escalate.25067501440118692527640914195751067314162057125172720293714026421375632375177
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3843833 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3843833 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3843833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_imem_err has 1 failures.

1.otbn_imem_err.102912661029177637233161749358833257728830767995129145734306952854871993893272
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_imem_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6982, which encodes to -3491, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

6.otbn_stress_all_with_rand_reset.90138511598861542487987026113278229902308962800054264931471555363083946414545
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5142, which encodes to -2571, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

9.otbn_escalate.47542894359506412686271773308489640028044260701345774132917327103942801728605
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  UVM_FATAL @  10991598 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10991598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.otbn_escalate.3604685289096187142606987801910729531431418270375892737877897569947607024382
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  UVM_FATAL @  18868744 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  18868744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.80599357139027888860379261080550653665222589445306449332282001967347547069955
    Line 386, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 101701036 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 101701036 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 101701036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.113392232550248560418280501122852655161028402273038033821738782164571112036221
    Line 383, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3148359121 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3148359121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 4.otbn_ctrl_redun.12213041989796307793067816691831528095652670048998766991946377019375849194587
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  61165024 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  61165024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 4.otbn_stack_addr_integ_chk.78073468449085098963202687821528987884231885253508151169938657385172443676328
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10057179151 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10057179151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.98499473010875356658588525329101654021552557222784431987588380902630505279400
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  11634169 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  11634169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 6.otbn_rf_base_intg_err.93093882692878958169672390479376479464409646356382469150946957819013488461625
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 1198803988 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 1198803988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_dv_otbn_sim_*/tb.sv,279): Assertion MatchingReqURND_A has failed has 1 failures:
- Test otbn_csr_mem_rw_with_rand_reset has 1 failures.
  - 10.otbn_csr_mem_rw_with_rand_reset.106980057708088180156511513586533075103109609090275446536156319390967817359395
    Line 272, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_csr_mem_rw_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/cover_reg_top/src/lowrisc_dv_otbn_sim_0.1/tb.sv,279): (time 183692817 PS) Assertion tb.MatchingReqURND_A has failed
  UVM_ERROR @ 183692817 ps: (tb.sv:279) [ASSERT FAILED] MatchingReqURND_A
  UVM_INFO @ 183692817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```