7773b039d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 160.983us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 26.185us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 18.215us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 8.000s | 53.825us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 20.419us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 15.000s | 64.109us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 18.215us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 20.419us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 38.000s | 356.522us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 24.000s | 723.339us | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 36.000s | 124.297us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 13.000s | 37.994us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 1.850m | 880.174us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.650m | 734.367us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 27.000s | 403.096us | 45 | 60 | 75.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 12.000s | 54.767us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 24.000s | 207.820us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 17.000s | 17.116us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 10.000s | 13.945us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 14.000s | 174.243us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 14.000s | 174.243us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 26.185us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 18.215us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 20.419us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 34.761us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 26.185us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 18.215us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 20.419us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 34.761us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 246 | 93.50 | |||
| V2S | mem_integrity | otbn_imem_err | 12.000s | 71.226us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 62.135us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 23.000s | 47.040us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 16.000s | 72.703us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 13.000s | 29.525us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 10.000s | 64.300us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 16.000s | 9.862us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 52.521us | 1 | 2 | 50.00 |
| V2S | tl_intg_err | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| otbn_tl_intg_err | 1.083m | 482.918us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 39.000s | 257.649us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | prim_count_check | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 160.983us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 62.135us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 12.000s | 71.226us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.083m | 482.918us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 27.000s | 403.096us | 45 | 60 | 75.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 12.000s | 71.226us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 62.135us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 54.767us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 16.000s | 9.862us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 71.226us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 62.135us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 54.767us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 16.000s | 9.862us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 27.000s | 403.096us | 45 | 60 | 75.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 12.000s | 71.226us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 62.135us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 54.767us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 16.000s | 9.862us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 14.000s | 34.087us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 68.668us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 30.000s | 487.190us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 30.000s | 487.190us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 13.000s | 322.515us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 13.000s | 64.662us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.050m | 10.001ms | 2 | 5 | 40.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.050m | 10.001ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 19.000s | 52.159us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.850m | 880.174us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 15.000s | 42.481us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 28.000s | 104.500us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 8.483m | 3.042ms | 4 | 5 | 80.00 |
| V2S | TOTAL | 146 | 153 | 95.42 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 9.450m | 26.021ms | 10 | 10 | 100.00 |
| V3 | TOTAL | 10 | 10 | 100.00 | |||
| TOTAL | 551 | 575 | 95.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 9 | 81.82 |
| V2S | 19 | 19 | 14 | 73.68 |
| V3 | 1 | 1 | 1 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.86 | 99.54 | 94.54 | 99.62 | 93.63 | 93.31 | 97.44 | 91.40 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:
17.otbn_escalate.7988528253892259413935348290589780885133844912265654590932936867881466857056
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 13593417 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 13593417 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 13593417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.otbn_escalate.105582486810219828262263515622567118091311262803370439181483243948318284013409
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/30.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4424061 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 4424061 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 4424061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_stack_addr_integ_chk has 2 failures.
3.otbn_stack_addr_integ_chk.29669666482057791782082849830463473628507610541907185643820247411295623296820
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11754444 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 11754444 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 11754444 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 11754444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_stack_addr_integ_chk.102606250440931013686413138344357964076265343316260000980435560888236043639767
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 251247311 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 251247311 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 251247311 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 251247311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 2 failures.
42.otbn_escalate.103939145637820328883044050631714486832565141363733834264953314943073529484294
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 26129443 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 26129443 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 26129443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.otbn_escalate.63096248859526475597747952349701493404388737238345074088368649728108990837294
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23219621 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 23219621 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 23219621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:
5.otbn_escalate.84274328723152258303722155180454221998901785020525633859467313446132669960195
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1276581 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1276581 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1276581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.otbn_escalate.58055469349628301221365759289323676704261803383654589855264173022274409053981
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4253671 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4253671 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4253671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_mem_gnt_acc_err has 1 failures.
1.otbn_mem_gnt_acc_err.110205947207452007495901660420827071076961526744622968750233653062058811857693
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_mem_gnt_acc_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6182, which encodes to -3091, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
75.otbn_single.35629212434516457896275510886334786420540775398119792447821950799837067461621
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/75.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6582, which encodes to -3291, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.50369621082810067869307638231635357818954206710798530409344039494969254571346
Line 375, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 37994302 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 37994302 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 37994302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.33251246342149957266893047043891992078123791517372232357551770879718984855525
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10000907551 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10000907551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
2.otbn_escalate.4748368074916630602204893966851192102821369984711776130849003873408323797853
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
UVM_FATAL @ 4223616 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 4223616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
2.otbn_ctrl_redun.64024435097755758613393580365313592435838089615792837047391374722096933081814
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 34086602 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 34086602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1295): Assertion SecWipeNonZeroMod_A has failed has 1 failures:
2.otbn_sec_cm.45839021791020830709921924176284863394622808998265493123108728185153629770094
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1295): (time 8351689 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1302): (time 8351689 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 8351689 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 8351689 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1256): (time 8351689 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
6.otbn_rf_base_intg_err.16404896756595319231516756875157353322862283738916773377224318820375284667611
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 222289034 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
UVM_INFO @ 222289034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
38.otbn_escalate.32135187967751350231411716674828355469447979779365291430083698353913680410200
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log
UVM_FATAL @ 3692480 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3692480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
40.otbn_escalate.49144722421910828735615193007946049903519207912364006965602965819448241259454
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log
UVM_FATAL @ 9967922 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 9967922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---