OTBN Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: `1f410ef5dc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	131.462us	1	1	100.00
V1	single_binary	otbn_single	44.000s	164.450us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	24.640us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	14.429us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	110.386us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	76.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	40.273us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	14.429us	20	20	100.00
		otbn_csr_aliasing	5.000s	76.807us	5	5	100.00
V1	mem_walk	otbn_mem_walk	49.000s	1.209ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	1.638ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	40.000s	129.667us	10	10	100.00
V2	multi_error	otbn_multi_err	27.000s	71.440us	0	1	0.00
V2	back_to_back	otbn_multi	2.983m	1.464ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.300m	246.760us	10	10	100.00
V2	lc_escalation	otbn_escalate	43.000s	158.183us	40	60	66.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	24.874us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	27.000s	110.306us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	22.081us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	25.499us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	837.300us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	837.300us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	24.640us	5	5	100.00
		otbn_csr_rw	6.000s	14.429us	20	20	100.00
		otbn_csr_aliasing	5.000s	76.807us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	30.651us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	24.640us	5	5	100.00
		otbn_csr_rw	6.000s	14.429us	20	20	100.00
		otbn_csr_aliasing	5.000s	76.807us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	30.651us	20	20	100.00
V2		TOTAL			224	246	91.06
V2S	mem_integrity	otbn_imem_err	13.000s	34.867us	10	10	100.00
		otbn_dmem_err	12.000s	218.607us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	84.048us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	214.164us	5	5	100.00
		otbn_mac_bignum_acc_err	26.000s	81.974us	5	5	100.00
		otbn_urnd_err	8.000s	20.349us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	17.684us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	5.165us	1	2	50.00
V2S	tl_intg_err	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
		otbn_tl_intg_err	45.000s	282.901us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	212.204us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	131.462us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	218.607us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	34.867us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	45.000s	282.901us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	43.000s	158.183us	40	60	66.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	34.867us	10	10	100.00
		otbn_dmem_err	12.000s	218.607us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.874us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.684us	5	5	100.00
		otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	34.867us	10	10	100.00
		otbn_dmem_err	12.000s	218.607us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.874us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.684us	5	5	100.00
		otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	43.000s	158.183us	40	60	66.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	34.867us	10	10	100.00
		otbn_dmem_err	12.000s	218.607us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	24.874us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	17.684us	5	5	100.00
		otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	66.968us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	150.113us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	270.875us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	270.875us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	38.813us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	154.879us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	105.485us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	105.485us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	54.000s	740.114us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.983m	1.464ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	34.594us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	44.000s	164.450us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	15.517m	7.223ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.317m	9.806ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			546	575	94.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.54	94.50	99.62	93.51	93.23	97.44	91.40	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 10 failures:

Test otbn_mem_gnt_acc_err has 1 failures.

0.otbn_mem_gnt_acc_err.43869688440074014942866569112564395844247400189193079794097092228882789758380
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 5165371 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   5165371 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   5165371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 9 failures.

4.otbn_escalate.28382627876979286676375273007704346264422154588701881893984473238653640408166
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 32458699 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32458699 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  32458699 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  32458699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.103184124372915729132664580277210007050890331835656471799733440470467509665389
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 11269401 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  11269401 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  11269401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 7 failures:

Test otbn_escalate has 7 failures.

2.otbn_escalate.66541701712318932966172522553688611771943884730579639425722529833202204327442
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6212506 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6212506 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6212506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.41187946973852718332876530023033040701904571782346585249541386425887707362687
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4644791 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4644791 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4644791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

23.otbn_escalate.34827833726774558130810100851662474279703972455958073988576376524551664461445
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  UVM_FATAL @  11832247 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11832247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.55771501695800720707437885424251926372893453056031193061690577205715243525331
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  UVM_FATAL @  18117922 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  18117922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.6301430957613383087507862891242100799575168668024142342439587615143789304841
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11289230 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 11289230 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  11289230 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11289230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

48.otbn_escalate.58836711759612220815698887480980471891319823973111124307780784176499504413597
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18184148 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18184148 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18184148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_multi has 1 failures.

1.otbn_multi.104882902097438296897037557257072898725256257891452649141885785274726721943662
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_multi/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6078, which encodes to -3039, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

3.otbn_stress_all_with_rand_reset.27063059677130262497117398141287674198101471062114281198158594685242569016861
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5946, which encodes to -2973, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.83672344094963691745786270128374686015627546387222402325118055746545296365420
    Line 388, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 71440106 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  71440106 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  71440106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.42096488026084914462054058734359281690863007423727858915013614691972162626632
    Line 355, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 262960530 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 262960530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.80559033680054263170158832184102009801028363431914479302326203216610661312867
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2362427787 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=0x2456001c)
  UVM_INFO @ 2362427787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 4.otbn_ctrl_redun.67805501547366985532633926874896339985765006969958850170297797157822412250238
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  49185509 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  49185509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.101750048042298755330978123414231594901797492020308427754861993471071640957165
    Line 323, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 356017689 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 356017689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```