OTBN Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	35.735us	1	1	100.00
V1	single_binary	otbn_single	1.417m	828.693us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	43.885us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	138.165us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	427.347us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	24.759us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	64.268us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	138.165us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.759us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	7.368ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	358.241us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.883m	515.577us	10	10	100.00
V2	multi_error	otbn_multi_err	34.000s	111.867us	0	1	0.00
V2	back_to_back	otbn_multi	16.417m	4.180ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.450m	540.174us	10	10	100.00
V2	lc_escalation	otbn_escalate	24.000s	185.487us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	51.542us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	33.000s	128.416us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	88.784us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	28.332us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	223.208us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	223.208us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	43.885us	5	5	100.00
		otbn_csr_rw	5.000s	138.165us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.759us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	59.711us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	43.885us	5	5	100.00
		otbn_csr_rw	5.000s	138.165us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.759us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	59.711us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	12.000s	50.808us	10	10	100.00
		otbn_dmem_err	12.000s	390.327us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	46.186us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	72.849us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	160.549us	5	5	100.00
		otbn_urnd_err	8.000s	15.503us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	10.197us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	13.131us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
		otbn_tl_intg_err	1.100m	474.462us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	34.000s	204.640us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	35.735us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	390.327us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	50.808us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.100m	474.462us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	24.000s	185.487us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	50.808us	10	10	100.00
		otbn_dmem_err	12.000s	390.327us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	51.542us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	10.197us	5	5	100.00
		otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	50.808us	10	10	100.00
		otbn_dmem_err	12.000s	390.327us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	51.542us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	10.197us	5	5	100.00
		otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	24.000s	185.487us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	50.808us	10	10	100.00
		otbn_dmem_err	12.000s	390.327us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	51.542us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	10.197us	5	5	100.00
		otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	40.553us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	22.360us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	296.937us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	296.937us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	40.917us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	231.727us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	40.000s	10.023ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	40.000s	10.023ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	71.639us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	16.417m	4.180ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	24.527us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.417m	828.693us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.450m	1.611ms	4	5	80.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.083m	10.191ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			551	575	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	8	72.73
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.53	94.46	99.61	93.57	93.35	94.87	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

3.otbn_escalate.43279535031144703951361352649266979095800217986423978109951358417828320257469
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 16385070 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16385070 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16385070 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  16385070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.73589067837189064150065791644678284247399304421569518969760316338414209725849
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4071503 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4071503 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4071503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_zero_state_err_urnd has 2 failures.

0.otbn_zero_state_err_urnd.104874223710485732498790199593507112091655844445222261550687245711240756690921
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19073075 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19073075 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19073075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_zero_state_err_urnd.96687885238444430419006854267421927017553761046457358211001160995821285621620
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11941832 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11941832 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11941832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

1.otbn_stack_addr_integ_chk.6868030986600598342593289240119270960427885654495673430719784827434310999101
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14368236 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14368236 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14368236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

59.otbn_escalate.51311810991265616673987051627071428254993812861124070001955153592361802619265
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/59.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23964059 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23964059 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23964059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

36.otbn_escalate.67831868647592090150420552541683956139074934284345652712319793664852022564982
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7644203 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7644203 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   7644203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.otbn_escalate.12756491630748167022145960554307387122247568637812716651022775398909888046269
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 870235 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @    870235 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @    870235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.65415480524208995148376118256525954088820770320546557593906738776947328188208
    Line 395, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 111866906 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 111866906 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 111866906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 0.otbn_ctrl_redun.17566300982667439014129026151163329716649567706892837823216779301505525399354
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @   9217381 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @   9217381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1297): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.68197523240188082146436558269424978065539872035331589502522896637644132099293
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1297): (time 2478966 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1304): (time 2478966 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2478966 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2478966 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 2478966 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.64214256501027923826613332664550839763277172602913769202598605859048920618914
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 865924455 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 865924455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 4.otbn_stack_addr_integ_chk.1319745054744455845645325219018182725470208483685444129262055382715007938831
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10023368095 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10023368095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.5459718800919877521007489189935623720069970238592100008580779471402079447246
    Line 424, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10190568061 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 10190568061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.1149757313105820999660162522051747119003114893597566043164439480820884146022
    Line 387, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1829939392 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1829939392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_single has 1 failures.

25.otbn_single.41154888498811409126544467396162031805373476480233317751923362066890381830856
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4786, which encodes to -2393, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 39.otbn_escalate.12533062797477578134167702071290873813200521177721590140497322028410292166043
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log
```
  UVM_FATAL @  13068781 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  13068781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```