OTBN Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	37.455us	1	1	100.00
V1	single_binary	otbn_single	2.517m	817.882us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	39.482us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	19.225us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	120.665us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	28.416us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	57.650us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	19.225us	20	20	100.00
		otbn_csr_aliasing	7.000s	28.416us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	1.789ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	1.788ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.083m	307.179us	10	10	100.00
V2	multi_error	otbn_multi_err	9.000s	44.699us	0	1	0.00
V2	back_to_back	otbn_multi	2.750m	1.033ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.683m	212.242us	10	10	100.00
V2	lc_escalation	otbn_escalate	49.000s	198.736us	43	60	71.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	23.734us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	57.000s	247.723us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	56.927us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	31.884us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	503.762us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	503.762us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	39.482us	5	5	100.00
		otbn_csr_rw	6.000s	19.225us	20	20	100.00
		otbn_csr_aliasing	7.000s	28.416us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	28.457us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	39.482us	5	5	100.00
		otbn_csr_rw	6.000s	19.225us	20	20	100.00
		otbn_csr_aliasing	7.000s	28.416us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	28.457us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	16.000s	41.876us	10	10	100.00
		otbn_dmem_err	16.000s	84.839us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	46.647us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	187.948us	3	5	60.00
		otbn_mac_bignum_acc_err	14.000s	63.087us	5	5	100.00
		otbn_urnd_err	13.000s	38.590us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	14.000s	50.191us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	27.730us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
		otbn_tl_intg_err	52.000s	356.033us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	50.000s	311.499us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	37.455us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	84.839us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	41.876us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	52.000s	356.033us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	49.000s	198.736us	43	60	71.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	41.876us	10	10	100.00
		otbn_dmem_err	16.000s	84.839us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.734us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	50.191us	5	5	100.00
		otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	41.876us	10	10	100.00
		otbn_dmem_err	16.000s	84.839us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.734us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	50.191us	5	5	100.00
		otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	49.000s	198.736us	43	60	71.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	41.876us	10	10	100.00
		otbn_dmem_err	16.000s	84.839us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	23.734us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	50.191us	5	5	100.00
		otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.200m	2.209ms	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	12.365us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	56.000s	2.687ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	56.000s	2.687ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	47.000s	172.877us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	237.063us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	10.003ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	43.000s	10.003ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	39.000s	150.509us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.750m	1.033ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	30.000s	239.557us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.517m	817.882us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.283m	2.825ms	5	5	100.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.683m	7.596ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			549	575	95.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	19	19	15	78.95
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.54	94.54	99.62	93.57	93.23	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

0.otbn_escalate.37720446989644692370104425199658279724903454384462240155241130184182638904620
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 42330134 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42330134 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42330134 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  42330134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_escalate.114652911814526333111971801801193451474111665728937090001243745772995962277149
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 40696147 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 40696147 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  40696147 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  40696147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

19.otbn_escalate.81987866381315325958820349359770876328063497267440438824045148824482079715836
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/19.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1282082 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   1282082 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   1282082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.124335894389872335548132469640415903677216898684723050702200903549796536669
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5845860 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5845860 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5845860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_controller_ispr_rdata_err has 1 failures.

3.otbn_controller_ispr_rdata_err.49849361511175986468480301556344133254458734060018685507827585819315216134746
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_controller_ispr_rdata_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -7590, which encodes to -3795, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

4.otbn_stress_all_with_rand_reset.40710262719968318209722881238048543036170537849061904845862159822982998387352
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6762, which encodes to -3381, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

72.otbn_single.71022167152120563426686582750912910142646816439112054947486505825935240010348
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/72.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4942, which encodes to -2471, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

20.otbn_escalate.20945244690597555695187894930053459401392659429667290229746845749623182187027
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  UVM_FATAL @  59755711 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  59755711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.otbn_escalate.37135412299382297156583643520922976198347368200349373910087894014606626134003
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  UVM_FATAL @  10974410 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10974410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

24.otbn_escalate.58381252714619576824602036824228853060136730699409895627592927723648017298579
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  UVM_FATAL @  14125267 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  14125267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.otbn_escalate.91373036469321712068744381289244501181168937617074175170341707912128463596282
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  UVM_FATAL @  81848831 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  81848831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.113485810160628392688090914344016352655165093142495115753220775567227630054191
    Line 370, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 44698877 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @  44698877 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @  44698877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_controller_ispr_rdata_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_controller_ispr_rdata_err has 1 failures.
  - 1.otbn_controller_ispr_rdata_err.49713638335942094175115578586640511318456088230862181503731691772290604731776
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_controller_ispr_rdata_err/latest/run.log
```
  UVM_FATAL @  29947601 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_controller_ispr_rdata_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  29947601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 2.otbn_stack_addr_integ_chk.79354893839464415443166674406511834884224406626375606244511576701026304255913
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10003335364 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10003335364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 3.otbn_rf_base_intg_err.38914468369958009102698767208048580050881165683321048864048146780064269110127
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 417938015 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
  UVM_INFO @ 417938015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.81203158517732604831131033712155992077740616069669907353088520186277751582631
    Line 451, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14581121618 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 14581121618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 8.otbn_ctrl_redun.80243334402638294455284709697808743043620968930421808996067590586791406051260
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @ 2209293106 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @ 2209293106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 14.otbn_escalate.106114765200290467913682840977073890934375099805291118206999359232750928214742
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61861568 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  61861568 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  61861568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```