OTBN Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	136.562us	1	1	100.00
V1	single_binary	otbn_single	1.467m	1.348ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	15.448us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.805us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	40.381us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	74.347us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	159.648us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.805us	20	20	100.00
		otbn_csr_aliasing	6.000s	74.347us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	7.437ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	360.595us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	29.000s	113.951us	10	10	100.00
V2	multi_error	otbn_multi_err	19.000s	114.656us	0	1	0.00
V2	back_to_back	otbn_multi	3.617m	977.601us	10	10	100.00
V2	stress_all	otbn_stress_all	1.267m	343.702us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.017m	242.140us	43	60	71.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	18.288us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	513.683us	10	10	100.00
V2	alert_test	otbn_alert_test	16.000s	15.576us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	22.986us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	703.984us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	703.984us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	15.448us	5	5	100.00
		otbn_csr_rw	6.000s	16.805us	20	20	100.00
		otbn_csr_aliasing	6.000s	74.347us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	32.317us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	15.448us	5	5	100.00
		otbn_csr_rw	6.000s	16.805us	20	20	100.00
		otbn_csr_aliasing	6.000s	74.347us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	32.317us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	14.000s	77.071us	10	10	100.00
		otbn_dmem_err	13.000s	34.484us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	260.033us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	84.860us	5	5	100.00
		otbn_mac_bignum_acc_err	29.000s	70.914us	5	5	100.00
		otbn_urnd_err	8.000s	28.250us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	15.648us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	38.295us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
		otbn_tl_intg_err	21.000s	421.037us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	919.627us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	136.562us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	34.484us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	77.071us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	21.000s	421.037us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.017m	242.140us	43	60	71.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	77.071us	10	10	100.00
		otbn_dmem_err	13.000s	34.484us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.288us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.648us	5	5	100.00
		otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	77.071us	10	10	100.00
		otbn_dmem_err	13.000s	34.484us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.288us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.648us	5	5	100.00
		otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.017m	242.140us	43	60	71.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	77.071us	10	10	100.00
		otbn_dmem_err	13.000s	34.484us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	18.288us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.648us	5	5	100.00
		otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	29.857us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	21.302us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.000m	263.128us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.000m	263.128us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	216.202us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	1.900m	555.056us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.050m	10.001ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.050m	10.001ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	26.180us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.617m	977.601us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	22.000s	53.941us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.467m	1.348ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.367m	2.261ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	24.433m	156.553ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			551	575	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.54	94.50	99.62	93.48	93.35	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

4.otbn_escalate.104150556552656780890044665277196871821916950305610605747511004601447925565336
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 164466138 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 164466138 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 164466138 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 164466138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.otbn_escalate.29774374367973614094980630856245020841621431119367116016434894861680505383980
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 52058121 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 52058121 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  52058121 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  52058121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:

Test otbn_escalate has 3 failures.

23.otbn_escalate.93374861086180042032243654332713361509664788395215773489275899491366564239427
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  UVM_FATAL @  26719661 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  26719661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.otbn_escalate.115626298454293143717998585975278848689826113818440525656807274101548700111701
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  UVM_FATAL @  10494329 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10494329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
- Test otbn_escalate has 2 failures.
  - 2.otbn_escalate.87761260091849520959183740345668159754690099826124564931776291729757656295076
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
```
  UVM_FATAL @   1497745 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   1497745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.otbn_escalate.16624511513234773050356251346043853209904306638757988385745928787857357698701
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log
```
  UVM_FATAL @   6261087 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   6261087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

26.otbn_escalate.72241425442890561926867609386146720082216849593147454966175232583097375913820
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3964151 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3964151 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3964151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.otbn_escalate.84910549377312013593191264297711186545341502841582197382781217292925186575902
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2345594 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   2345594 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   2345594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): (time * NS) Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.58206917926205674130989812572076804439635658341597874684156754900143160887406
    Line 384, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 114656 NS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 114656000 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 114656000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.36143137235603431100373899710678630279129696953548867043578822183860252378875
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10000976844 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10000976844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.80770359928207769580038314504002902305590649314029955543922062910279316114800
    Line 426, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2528687238 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2528687238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 3.otbn_ctrl_redun.60785026328350366414462811722475647354044176624597428304772524294063781291914
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  14673553 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  14673553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

5.otbn_stress_all_with_rand_reset.80485484157668421536326581150506240767064702744874937593930537793418149042168
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4286, which encodes to -2143, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 6.otbn_escalate.76320354582680874226972006326592115839492167632258446323334895069970188869683
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
```
  UVM_FATAL @  16580452 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  16580452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.71837785958906175424790616933485771276378358418979735281515380755529658971594
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  21093761 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  21093761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.77673479091050977154028320326807870459682663646191182357881281182118046196382
    Line 465, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3472349916 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3472349916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 46.otbn_escalate.61219634848948364262904387544140660362176050842649960091828835944376548436703
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/46.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 100624064 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 100624064 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 100624064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```