OTBN Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 37.006us 1 1 100.00
V1 single_binary otbn_single 31.000s 166.712us 99 100 99.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 23.833us 5 5 100.00
V1 csr_rw otbn_csr_rw 5.000s 38.830us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 135.259us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 313.917us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 447.130us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 38.830us 20 20 100.00
otbn_csr_aliasing 6.000s 313.917us 5 5 100.00
V1 mem_walk otbn_mem_walk 47.000s 5.635ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 22.000s 1.094ms 5 5 100.00
V1 TOTAL 165 166 99.40
V2 reset_recovery otbn_reset 30.000s 167.931us 10 10 100.00
V2 multi_error otbn_multi_err 23.000s 61.526us 0 1 0.00
V2 back_to_back otbn_multi 2.583m 3.294ms 9 10 90.00
V2 stress_all otbn_stress_all 1.367m 298.676us 10 10 100.00
V2 lc_escalation otbn_escalate 5.583m 1.547ms 46 60 76.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 50.986us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 21.000s 52.287us 10 10 100.00
V2 alert_test otbn_alert_test 8.000s 21.538us 50 50 100.00
V2 intr_test otbn_intr_test 5.000s 19.538us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 10.000s 454.872us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 10.000s 454.872us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 23.833us 5 5 100.00
otbn_csr_rw 5.000s 38.830us 20 20 100.00
otbn_csr_aliasing 6.000s 313.917us 5 5 100.00
otbn_same_csr_outstanding 6.000s 219.450us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 23.833us 5 5 100.00
otbn_csr_rw 5.000s 38.830us 20 20 100.00
otbn_csr_aliasing 6.000s 313.917us 5 5 100.00
otbn_same_csr_outstanding 6.000s 219.450us 20 20 100.00
V2 TOTAL 229 246 93.09
V2S mem_integrity otbn_imem_err 16.000s 203.675us 10 10 100.00
otbn_dmem_err 15.000s 50.577us 15 15 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 45.000s 201.432us 5 5 100.00
otbn_controller_ispr_rdata_err 10.000s 69.085us 5 5 100.00
otbn_mac_bignum_acc_err 12.000s 77.548us 5 5 100.00
otbn_urnd_err 8.000s 16.952us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 67.481us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 21.409us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 9.350m 2.952ms 5 5 100.00
otbn_tl_intg_err 36.000s 270.229us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 34.000s 199.600us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S prim_count_check otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 37.006us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 15.000s 50.577us 15 15 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 16.000s 203.675us 10 10 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 36.000s 270.229us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 5.583m 1.547ms 46 60 76.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 16.000s 203.675us 10 10 100.00
otbn_dmem_err 15.000s 50.577us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.986us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.481us 5 5 100.00
otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_scramble_key_sideload otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 16.000s 203.675us 10 10 100.00
otbn_dmem_err 15.000s 50.577us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.986us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.481us 5 5 100.00
otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 5.583m 1.547ms 46 60 76.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 16.000s 203.675us 10 10 100.00
otbn_dmem_err 15.000s 50.577us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.986us 4 5 80.00
otbn_illegal_mem_acc 8.000s 67.481us 5 5 100.00
otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 12.000s 32.109us 8 12 66.67
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 14.000s 61.160us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 53.000s 484.491us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 53.000s 484.491us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 12.000s 1.375ms 8 10 80.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 14.000s 75.443us 10 10 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 47.000s 10.004ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 47.000s 10.004ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 19.000s 60.812us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_write_mem_integrity otbn_multi 2.583m 3.294ms 9 10 90.00
V2S sec_cm_ctrl_flow_count otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_ctrl_flow_sca otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 10.000s 75.207us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 31.000s 166.712us 99 100 99.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 9.350m 2.952ms 5 5 100.00
V2S TOTAL 145 153 94.77
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 10.433m 8.664ms 8 10 80.00
V3 TOTAL 8 10 80.00
TOTAL 547 575 95.13

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 7 63.64
V2S 19 19 16 84.21
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.83 99.50 93.98 99.58 93.52 93.51 94.87 90.91 99.16

Failure Buckets

Past Results