d0c52cdadd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 37.006us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 23.833us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 5.000s | 38.830us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 135.259us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 313.917us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 8.000s | 447.130us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 5.000s | 38.830us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 313.917us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 47.000s | 5.635ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 22.000s | 1.094ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 30.000s | 167.931us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 23.000s | 61.526us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 2.583m | 3.294ms | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 1.367m | 298.676us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 5.583m | 1.547ms | 46 | 60 | 76.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 50.986us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 21.000s | 52.287us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 21.538us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 5.000s | 19.538us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 454.872us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 454.872us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 23.833us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 38.830us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 313.917us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 219.450us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 23.833us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 38.830us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 313.917us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 219.450us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 229 | 246 | 93.09 | |||
| V2S | mem_integrity | otbn_imem_err | 16.000s | 203.675us | 10 | 10 | 100.00 |
| otbn_dmem_err | 15.000s | 50.577us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 45.000s | 201.432us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 10.000s | 69.085us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 77.548us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 16.952us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 67.481us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 21.409us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 36.000s | 270.229us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 34.000s | 199.600us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 37.006us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 15.000s | 50.577us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 16.000s | 203.675us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 36.000s | 270.229us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 5.583m | 1.547ms | 46 | 60 | 76.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 16.000s | 203.675us | 10 | 10 | 100.00 |
| otbn_dmem_err | 15.000s | 50.577us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 50.986us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 67.481us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 16.000s | 203.675us | 10 | 10 | 100.00 |
| otbn_dmem_err | 15.000s | 50.577us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 50.986us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 67.481us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 5.583m | 1.547ms | 46 | 60 | 76.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 16.000s | 203.675us | 10 | 10 | 100.00 |
| otbn_dmem_err | 15.000s | 50.577us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 50.986us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 67.481us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 12.000s | 32.109us | 8 | 12 | 66.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 14.000s | 61.160us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 53.000s | 484.491us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 53.000s | 484.491us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 1.375ms | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 75.443us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 47.000s | 10.004ms | 3 | 5 | 60.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 47.000s | 10.004ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 19.000s | 60.812us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.583m | 3.294ms | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 10.000s | 75.207us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 31.000s | 166.712us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 9.350m | 2.952ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 145 | 153 | 94.77 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 10.433m | 8.664ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 547 | 575 | 95.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 16 | 84.21 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.83 | 99.50 | 93.98 | 99.58 | 93.52 | 93.51 | 94.87 | 90.91 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:
9.otbn_escalate.55431423419886972663844757874079526169031716250892267748236902177185455364829
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7516268 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7516268 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7516268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.otbn_escalate.62445430813704097449256554670295586564755922549368022431018856419274150112261
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 33693246 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33693246 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 33693246 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 33693246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_zero_state_err_urnd has 1 failures.
3.otbn_zero_state_err_urnd.336631257118260832079952283565622745043889654369622742140622963223986211649
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50004667 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 50004667 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 50004667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stack_addr_integ_chk has 1 failures.
4.otbn_stack_addr_integ_chk.81400316291435712201444373494323418832863104282142216202337753804375119109910
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 73459449 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 73459449 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 73459449 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 73459449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_ctrl_redun has 1 failures.
5.otbn_ctrl_redun.9460954437761910857096703876220771251909629032256533102869826344696460489201
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10903814 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 10903814 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 10903814 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10903814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 2 failures.
15.otbn_escalate.64951062561000912752775561842016028028569915756894847526100070800323521350178
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 471961347 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 471961347 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 471961347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.otbn_escalate.87779971902916829901106712322769171355821143723136656886615853967345080208503
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/34.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 67313244 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 67313244 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 67313244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 3 failures:
2.otbn_ctrl_redun.96745514956346631524606641024295607058046590223433171549290106436033102978479
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 12543027 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 12543027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_ctrl_redun.7691783269503529079210175820943700773057100965099424196928839531723007597025
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 39359897 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 39359897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_multi has 1 failures.
0.otbn_multi.22726968179369151482747958594535042718023874126768177848509232037172888448107
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6354, which encodes to -3177, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
40.otbn_single.17991330473699370026912371811892520419389219477099368162734133196314461354084
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4682, which encodes to -2341, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
0.otbn_stress_all_with_rand_reset.36535380843100660158414893748936576918377996377781756621690391609448661373265
Line 397, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 723304431 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 723304431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_stress_all_with_rand_reset.964997795704420245778616654954054609141566181809647835704363476093593417661
Line 346, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 889719056 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 889719056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
16.otbn_escalate.48123443391352866682222221684143945927919143507920617743701533302161262597307
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
UVM_FATAL @ 25950911 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 25950911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.otbn_escalate.13927962035141391891480317049670236469433108813712939363622997155411718096299
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
UVM_FATAL @ 100943891 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 100943891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.62009935867205318676082615803740433897918946616865547582989193648595206349776
Line 382, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 61525647 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 61525647 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 61525647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:96) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
2.otbn_rf_base_intg_err.2724272632116147145902927492771362804541474691987314574597410462284198355043
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 32864412 ps: (otbn_rf_base_intg_err_vseq.sv:96) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 32864412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
3.otbn_escalate.15411160372727247744819917049855929194124471556582856683931074225897667233259
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
UVM_FATAL @ 14456069 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 14456069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
3.otbn_rf_base_intg_err.53238240255110376435766577685075711613769127789726841356878053488596554204911
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 1375042185 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
UVM_INFO @ 1375042185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:58) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
3.otbn_stack_addr_integ_chk.92212981571740323067136263349395984611856394007740181347314531031100544533472
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10003893341 ps: (otbn_stack_addr_integ_chk_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10003893341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
7.otbn_escalate.44954946144056277042605270119164539249544817263371155668409805565250454134034
Line 302, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 2962766 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 2962766 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 2962766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---