18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 38.162us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 13.508us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 11.000s | 17.824us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 8.000s | 129.312us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 21.317us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 71.232us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 11.000s | 17.824us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 21.317us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 50.000s | 1.878ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 19.000s | 477.628us | 5 | 5 | 100.00 |
| V1 | TOTAL | 164 | 166 | 98.80 | |||
| V2 | reset_recovery | otbn_reset | 32.000s | 481.350us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 16.000s | 547.564us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 1.750m | 985.844us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.533m | 382.636us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 28.000s | 202.547us | 44 | 60 | 73.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 16.620us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 11.000s | 72.277us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 40.723us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 8.000s | 28.066us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 62.972us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 62.972us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 13.508us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 17.824us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 21.317us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 21.852us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 13.508us | 5 | 5 | 100.00 |
| otbn_csr_rw | 11.000s | 17.824us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 21.317us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 21.852us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 229 | 246 | 93.09 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 41.939us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 46.137us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 17.000s | 39.326us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 13.000s | 45.867us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 11.000s | 44.898us | 4 | 5 | 80.00 | ||
| otbn_urnd_err | 9.000s | 149.713us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 36.778us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 31.184us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 1.150m | 474.214us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 42.000s | 231.234us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 38.162us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 13.000s | 46.137us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 41.939us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.150m | 474.214us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 28.000s | 202.547us | 44 | 60 | 73.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 41.939us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 46.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.620us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 36.778us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 41.939us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 46.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.620us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 36.778us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 28.000s | 202.547us | 44 | 60 | 73.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 41.939us | 10 | 10 | 100.00 |
| otbn_dmem_err | 13.000s | 46.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.620us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 7.000s | 36.778us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 64.278us | 9 | 12 | 75.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 10.000s | 23.059us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 44.000s | 450.653us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 44.000s | 450.653us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 878.943us | 8 | 10 | 80.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 15.000s | 83.794us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 34.000s | 10.071ms | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 34.000s | 10.071ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 11.000s | 29.558us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.750m | 985.844us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 20.000s | 35.382us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.100m | 277.047us | 98 | 100 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 7.967m | 2.659ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 146 | 153 | 95.42 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 9.400m | 6.319ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 547 | 575 | 95.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 9 | 81.82 |
| V2S | 19 | 19 | 15 | 78.95 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.82 | 99.53 | 94.46 | 99.61 | 93.52 | 92.85 | 97.44 | 91.38 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:
3.otbn_escalate.39824920070472641130350878057517989102811160402978883259989185113643882182096
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 221923767 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 221923767 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 221923767 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 221923767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.otbn_escalate.43640229892295819780841065970837369435423810138327923322881845205046521568045
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 26473053 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 26473053 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 26473053 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 26473053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_ctrl_redun has 2 failures.
3.otbn_ctrl_redun.87321226117745687747982190912334939465375248400454537779183533093318906198632
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13301003 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 13301003 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 13301003 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13301003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_ctrl_redun.74342328806384781262386407181035581770533482535293146512094692375212199176646
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36417804 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 36417804 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 36417804 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 36417804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
21.otbn_escalate.71264012084765825696490616049334941076946752028896608790818305163789476427709
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13311678 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 13311678 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13311678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.otbn_escalate.91053142914548278242608466717840334522898596157536218801736068463264499468815
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 37240327 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 37240327 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 37240327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
Test otbn_mac_bignum_acc_err has 1 failures.
0.otbn_mac_bignum_acc_err.99126615156465641150509988420823030233608896652225379723575533569620828714830
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6494, which encodes to -3247, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_escalate has 1 failures.
29.otbn_escalate.34271167408994545336100895519407084474716751827105377867823719227379919697895
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6150, which encodes to -3075, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
45.otbn_single.43181445334113139004422676855294164260555002621787628282410409136419873363057
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6670, which encodes to -3335, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
6.otbn_escalate.15089046910166810816674646549815525239366035067349339908955300521572312851870
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1265320 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1265320 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1265320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.otbn_escalate.76428754841619791047682485861029225371639412973601369480292181135755952611328
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4030491 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4030491 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4030491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
20.otbn_escalate.74378936155840115182851349296631600095391622853568700781565038902418570369363
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
UVM_FATAL @ 7661981 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 7661981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.otbn_escalate.31191997700110269897727159768782337277389250508836810890974499040169416621839
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log
UVM_FATAL @ 51863262 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 51863262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.59807176651503321539480729336381349821603673818144131424773603602217040547636
Line 382, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 547564238 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 547564238 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 547564238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
0.otbn_stress_all_with_rand_reset.833317567850331861562629118819899023933351038194967003281840968199851373365
Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11691176 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 11691176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
2.otbn_stack_addr_integ_chk.111687891591404955641139775090835520103733682607068806696030007437690680736160
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10071039645 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10071039645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used has 1 failures:
3.otbn_rf_base_intg_err.25307361168203702001489457762300556481902323773606583105243262079545912288589
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 1215108827 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file B to be used
UVM_INFO @ 1215108827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_ctrl_redun_vseq.sv:31) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
6.otbn_ctrl_redun.28136138622002849355233909844738706021030573751492987019182334083701651374479
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log
UVM_FATAL @ 66344748 ps: (otbn_ctrl_redun_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
UVM_INFO @ 66344748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:32) virtual_sequencer [otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used has 1 failures:
8.otbn_rf_base_intg_err.48604893689248655007388584541705396486849879212645996311834687168297565719071
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 878943411 ps: (otbn_rf_base_intg_err_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Timeout while waiting for register file A to be used
UVM_INFO @ 878943411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
8.otbn_stress_all_with_rand_reset.34188989514838497397791767318244722212965208480436065278434105530657944390128
Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 283313126 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 283313126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
31.otbn_escalate.58944614285103414681473441392240545279077181056524462857764677239821229637986
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log
UVM_FATAL @ 3336920 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 3336920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
42.otbn_escalate.60856813925532917436764469343934375000222313594770812359828197406020548696584
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/42.otbn_escalate/latest/run.log
UVM_FATAL @ 20607811 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 20607811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,862): Assertion NotBusyAndDone_A has failed has 1 failures:
77.otbn_single.68217404568340517773468842398818756270180631671092385790827082555947805357709
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/77.otbn_single/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,862): (time 49766390 PS) Assertion tb.dut.NotBusyAndDone_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1347): (time 49766390 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 49766390 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 49766390 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 49766390 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed