OTBN Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	132.683us	1	1	100.00
V1	single_binary	otbn_single	1.167m	290.593us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	17.447us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	13.158us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	454.750us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	33.065us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	60.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	13.158us	20	20	100.00
		otbn_csr_aliasing	5.000s	33.065us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	17.134ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	361.969us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.483m	704.616us	10	10	100.00
V2	multi_error	otbn_multi_err	35.000s	102.412us	0	1	0.00
V2	back_to_back	otbn_multi	1.217m	978.674us	10	10	100.00
V2	stress_all	otbn_stress_all	1.450m	3.726ms	10	10	100.00
V2	lc_escalation	otbn_escalate	46.000s	395.909us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	20.702us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	34.473us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	45.697us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	35.502us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	437.713us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	437.713us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	17.447us	5	5	100.00
		otbn_csr_rw	6.000s	13.158us	20	20	100.00
		otbn_csr_aliasing	5.000s	33.065us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.487us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	17.447us	5	5	100.00
		otbn_csr_rw	6.000s	13.158us	20	20	100.00
		otbn_csr_aliasing	5.000s	33.065us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	26.487us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	12.000s	24.134us	10	10	100.00
		otbn_dmem_err	19.000s	72.443us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	203.918us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	108.681us	4	5	80.00
		otbn_mac_bignum_acc_err	11.000s	64.390us	5	5	100.00
		otbn_urnd_err	8.000s	22.328us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	68.076us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	45.946us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
		otbn_tl_intg_err	1.467m	598.589us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	53.000s	289.042us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	132.683us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	72.443us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	24.134us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.467m	598.589us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	46.000s	395.909us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	24.134us	10	10	100.00
		otbn_dmem_err	19.000s	72.443us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.702us	3	5	60.00
		otbn_illegal_mem_acc	8.000s	68.076us	5	5	100.00
		otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	24.134us	10	10	100.00
		otbn_dmem_err	19.000s	72.443us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.702us	3	5	60.00
		otbn_illegal_mem_acc	8.000s	68.076us	5	5	100.00
		otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	46.000s	395.909us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	24.134us	10	10	100.00
		otbn_dmem_err	19.000s	72.443us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	20.702us	3	5	60.00
		otbn_illegal_mem_acc	8.000s	68.076us	5	5	100.00
		otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	30.320us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	25.953us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	40.000s	127.833us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	40.000s	127.833us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	47.280us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	366.656us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	95.742us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	95.742us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	1.017m	798.926us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.217m	978.674us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	47.000s	226.102us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.167m	290.593us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.633m	2.019ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	14.450m	11.158ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			551	575	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	8	72.73
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.85	99.51	94.07	99.60	93.49	93.69	97.44	90.91	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_zero_state_err_urnd has 2 failures.

2.otbn_zero_state_err_urnd.8314111029243835521909152010626451544545069446298363737465801693264792601756
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 82418289 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  82418289 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  82418289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_zero_state_err_urnd.112700499344694429040694294433219355353107129503382444950975421955399610857522
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8513349 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   8513349 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8513349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.101002487868167170797616428550032870228707737728631542039159047285833407652842
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60455302 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 60455302 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  60455302 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  60455302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

11.otbn_ctrl_redun.70463970084410463591134419462836948228491733424119211673791566586210934360706
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17214651 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 17214651 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  17214651 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17214651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

23.otbn_escalate.85002622561957159529662177427545513176078172325728252625177811423361896315307
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 395908684 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 395908684 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 395908684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.otbn_escalate.35065155960406479952185853747213654770292795064845347598056337485457964574127
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21881221 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21881221 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21881221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:

Test otbn_escalate has 5 failures.

7.otbn_escalate.113983874168268152279909845385734133455928412745042350398154108035572195841840
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 14122096 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  14122096 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  14122096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.36975396699070015163829262951102541724054912322947746389864560745618000602909
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 7431166 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   7431166 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   7431166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 5.otbn_stress_all_with_rand_reset.44161347800730262645324397148169434162994659123193080170572277988906009383089
    Line 382, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4097131681 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4097131681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.113547971800083118852451027960825934817679204522657933873897974822949053042968
    Line 492, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2100510120 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2100510120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

12.otbn_escalate.78909866922025329636993987779385608134172712495323713047861336631988027778136
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  UVM_FATAL @  19338695 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  19338695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.otbn_escalate.48283341847762397950311023612971751607236841993684411562307515094799893745480
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  UVM_FATAL @  38339894 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  38339894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

26.otbn_escalate.55758809792539805474660204193940749042081173148187664540701024294136469925249
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3855896 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3855896 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3855896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.otbn_escalate.33732203643034846905182956970602042022201708728747229013979059014065493116397
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/45.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4379806 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4379806 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   4379806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,950): Assertion ImemAddrOKnown_A has failed has 1 failures:
- Test otbn_multi_err has 1 failures.
  - 0.otbn_multi_err.98152513463805177182997074493609388323975690590586308961342734842909454354511
    Line 394, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 102412294 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
  UVM_ERROR @ 102412294 ps: (otbn_core.sv:950) [ASSERT FAILED] ImemAddrOKnown_A
  UVM_INFO @ 102412294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_controller_ispr_rdata_err has 1 failures.

1.otbn_controller_ispr_rdata_err.2744575906441819843645748687188190276065729247151293327300337322996592560238
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_controller_ispr_rdata_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4766, which encodes to -2383, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.9557138759462588482668737777269158887076268771940561387761042245268932981573
    Line 476, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11227547179 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 11227547179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.111418371516130343977587865561304839907623228017826575813280474363395432503591
    Line 533, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11157828014 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11157828014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:754) [otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.13451619732735609602459872830301140406691346545896300598100939883162430825060
    Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  79761318 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  79761318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 27.otbn_escalate.32524143674541125817656180524227057276186690153187697555932288128708568649269
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log
```
  UVM_FATAL @  15215321 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  15215321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 57.otbn_escalate.11577398464708318154951680572162270522297622517526873342153498899545539565098
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/57.otbn_escalate/latest/run.log
```
  UVM_FATAL @   8387783 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   8387783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```