3e678c112b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 11.000s | 39.499us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 9.000s | 40.842us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 7.000s | 23.199us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 10.000s | 1.817ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 51.878us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 12.000s | 44.545us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 7.000s | 23.199us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 51.878us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 59.000s | 3.648ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 28.000s | 2.742ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 1.167m | 323.036us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 46.000s | 452.658us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.817m | 209.807us | 9 | 10 | 90.00 |
| V2 | stress_all | otbn_stress_all | 2.083m | 1.814ms | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 55.000s | 237.563us | 49 | 60 | 81.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 23.121us | 3 | 5 | 60.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 18.000s | 65.879us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 23.550us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 19.027us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 11.000s | 132.365us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 11.000s | 132.365us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 9.000s | 40.842us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 23.199us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 51.878us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 48.434us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 9.000s | 40.842us | 5 | 5 | 100.00 |
| otbn_csr_rw | 7.000s | 23.199us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 51.878us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 9.000s | 48.434us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 246 | 93.50 | |||
| V2S | mem_integrity | otbn_imem_err | 16.000s | 75.075us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 24.826us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 12.000s | 106.345us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 36.000s | 287.961us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 91.647us | 4 | 5 | 80.00 | ||
| otbn_urnd_err | 8.000s | 14.833us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 7.000s | 118.036us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 15.000s | 57.110us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 9.000s | 26.040us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 28.000s | 185.495us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 37.000s | 204.758us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 11.000s | 39.499us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 12.000s | 24.826us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 16.000s | 75.075us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 28.000s | 185.495us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 55.000s | 237.563us | 49 | 60 | 81.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 16.000s | 75.075us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 24.826us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.121us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 118.036us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 16.000s | 75.075us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 24.826us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.121us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 118.036us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 55.000s | 237.563us | 49 | 60 | 81.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 16.000s | 75.075us | 10 | 10 | 100.00 |
| otbn_dmem_err | 12.000s | 24.826us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 9.000s | 23.121us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 7.000s | 118.036us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 24.827us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 53.119us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.200m | 455.737us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.200m | 455.737us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 19.000s | 77.740us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 92.080us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 16.000s | 438.085us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 16.000s | 438.085us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 14.000s | 109.261us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.817m | 209.807us | 9 | 10 | 90.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 27.000s | 354.037us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.017m | 262.611us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 3.833m | 991.632us | 5 | 5 | 100.00 |
| V2S | TOTAL | 160 | 163 | 98.16 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 15.817m | 2.567ms | 10 | 10 | 100.00 |
| V3 | TOTAL | 10 | 10 | 100.00 | |||
| TOTAL | 565 | 585 | 96.58 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 20 | 20 | 17 | 85.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.90 | 99.62 | 95.62 | 99.70 | 93.55 | 92.59 | 97.44 | 91.61 | 99.16 |
Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:
Test otbn_stress_all has 2 failures.
1.otbn_stress_all.7593464581672284971890071764588712498793950691202864079642507837764637335826
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4110, which encodes to -2055, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
3.otbn_stress_all.39131479989368371413187326123726479427530431886852579288881912467169010117028
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4722, which encodes to -2361, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_multi has 1 failures.
3.otbn_multi.111264575753608310052165726058933507280010027570226987413612207832703305331868
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_multi/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -7462, which encodes to -3731, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_escalate has 2 failures.
38.otbn_escalate.63719741909129519919942380546291671634952259821090376101820152861058231729206
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/38.otbn_escalate/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5474, which encodes to -2737, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
49.otbn_escalate.35274292005896255131238290886818029692508275889917293496546254313525259428615
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5662, which encodes to -2831, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
88.otbn_single.66338473958714815973691892069812291860364768708411879865326295954885966297947
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/88.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -4218, which encodes to -2109, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_zero_state_err_urnd has 2 failures.
1.otbn_zero_state_err_urnd.56599878238464055384448796109715756864043177702045682005655471739358914899520
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12821271 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 12821271 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 12821271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_zero_state_err_urnd.17515425491335372485471433926587159871436892825885556249198714552550042407767
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32001342 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 32001342 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 32001342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
8.otbn_escalate.36345177563429858529234751001251391252120194941367054178327341130843143778945
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22229756 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 22229756 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22229756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.otbn_escalate.88849426164967238353374398715874199179235604338007229829266487742688943325083
Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61686072 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 61686072 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 61686072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
15.otbn_escalate.46823151802287694018464514641306653365593761502765491632413663822957678077541
Line 307, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 21900011 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 21900011 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 21900011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
50.otbn_escalate.45023597053210186456555478734981349863281492311170656597130228923033588541728
Line 304, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/50.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 22073721 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 22073721 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 22073721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 3 failures:
36.otbn_escalate.40161652211620152590831992062320752875665451631826850337164532788616799168395
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4009920 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 4009920 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 4009920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.otbn_escalate.103144142035805834287716854700094324624426618458219262870574846997012901486409
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1126867 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 1126867 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 1126867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:198) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
0.otbn_partial_wipe.74691645490728090058937053061534127742966433768291100726839677958056530513632
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log
UVM_FATAL @ 16549678 ps: (otbn_scoreboard.sv:198) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
UVM_INFO @ 16549678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_mac_bignum_acc_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
1.otbn_mac_bignum_acc_err.70540171237297754004525304334346439303240166910627437077344173742418100949684
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest/run.log
UVM_FATAL @ 36179797 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_mac_bignum_acc_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 36179797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
4.otbn_rf_base_intg_err.44010906685600782720111475458601411752743821719549137550888478872384766235099
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 54560373 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 54560373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---