OTBN Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	312.810us	1	1	100.00
V1	single_binary	otbn_single	55.000s	225.431us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	27.249us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	45.441us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	97.336us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	30.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	104.252us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	45.441us	20	20	100.00
		otbn_csr_aliasing	7.000s	30.669us	5	5	100.00
V1	mem_walk	otbn_mem_walk	52.000s	1.784ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	149.768us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	42.000s	215.619us	10	10	100.00
V2	multi_error	otbn_multi_err	56.000s	565.045us	1	1	100.00
V2	back_to_back	otbn_multi	1.367m	524.559us	10	10	100.00
V2	stress_all	otbn_stress_all	1.550m	366.168us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.117m	994.043us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	49.746us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	83.744us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	24.414us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	20.160us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	56.653us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	56.653us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	27.249us	5	5	100.00
		otbn_csr_rw	6.000s	45.441us	20	20	100.00
		otbn_csr_aliasing	7.000s	30.669us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	45.119us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	27.249us	5	5	100.00
		otbn_csr_rw	6.000s	45.441us	20	20	100.00
		otbn_csr_aliasing	7.000s	30.669us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	45.119us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	13.000s	110.780us	9	10	90.00
		otbn_dmem_err	12.000s	20.203us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	171.953us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	28.677us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	78.985us	5	5	100.00
		otbn_urnd_err	6.000s	12.950us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	20.330us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	22.548us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	49.408us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
		otbn_tl_intg_err	30.000s	192.550us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	167.401us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	312.810us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	20.203us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	110.780us	9	10	90.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	30.000s	192.550us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.117m	994.043us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	110.780us	9	10	90.00
		otbn_dmem_err	12.000s	20.203us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	49.746us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.330us	5	5	100.00
		otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	110.780us	9	10	90.00
		otbn_dmem_err	12.000s	20.203us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	49.746us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.330us	5	5	100.00
		otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.117m	994.043us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	110.780us	9	10	90.00
		otbn_dmem_err	12.000s	20.203us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	49.746us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	20.330us	5	5	100.00
		otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	24.314us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	14.869us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	48.000s	227.784us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	48.000s	227.784us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	71.904us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	64.721us	9	10	90.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.233m	2.178ms	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.233m	2.178ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	26.000s	732.752us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.367m	524.559us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	72.756us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	55.000s	225.431us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.783m	3.527ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.167m	84.567ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			569	585	97.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.60	95.40	99.69	93.46	92.54	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

7.otbn_escalate.18990419376630090254770880790206335821882530465755476483682212085910304992198
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 42446309 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42446309 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42446309 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  42446309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.otbn_escalate.78110496384882339394663523184509278246249908929296619455558361603960579644050
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/26.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6394194 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6394194 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6394194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

4.otbn_stress_all_with_rand_reset.52234115879894771481345647966583351294688550876220109972517031667522061465131
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5470, which encodes to -2735, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_rf_bignum_intg_err has 1 failures.

5.otbn_rf_bignum_intg_err.90990165638135074172511830195938607585032332147261228836259144930387013419786
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_rf_bignum_intg_err/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4946, which encodes to -2473, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

77.otbn_single.63828870705444158576386582926430037158179638231002597185368260150379692691325
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/77.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4170, which encodes to -2085, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

20.otbn_escalate.43225003975124405534546314363637440497395390900857837367720963264471540870567
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 81086523 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  81086523 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  81086523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

56.otbn_escalate.60471081712498838382701367005172274966084336698188548121452963986406125151688
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/56.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18712917 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18712917 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18712917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.25971371437796753523584322646699745387774452209345303584086060713754848129257
    Line 445, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_rnd_if.sv,175): (time 3378264631 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if.EdgePREFETCHINGToFULL_A has failed (2 cycles, starting 3378193202 PS)
  UVM_ERROR @ 3378264631 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
  UVM_INFO @ 3378264631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_imem_err has 1 failures.
  - 8.otbn_imem_err.63112232705372081410600904795120176799988094337948523401552384001622105446355
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_imem_err/latest/run.log
```
  UVM_FATAL @  25607305 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  25607305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 8.otbn_partial_wipe.89983171707407905029266499513521507310596744920628930837158080495020339401924
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7056552 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7056552 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7056552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 10.otbn_escalate.445064922911159568239347884718493047626208494502729582354567265601480487237
    Line 307, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 174138053 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @ 174138053 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @ 174138053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```