OTBN Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	611.247us	1	1	100.00
V1	single_binary	otbn_single	2.033m	501.864us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	48.922us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.120us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	91.915us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	134.374us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	31.918us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.120us	20	20	100.00
		otbn_csr_aliasing	5.000s	134.374us	5	5	100.00
V1	mem_walk	otbn_mem_walk	45.000s	1.932ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	720.924us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	50.000s	187.654us	10	10	100.00
V2	multi_error	otbn_multi_err	1.950m	543.951us	1	1	100.00
V2	back_to_back	otbn_multi	4.867m	1.271ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.100m	352.368us	8	10	80.00
V2	lc_escalation	otbn_escalate	15.000s	94.337us	52	60	86.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	15.756us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	15.000s	151.138us	10	10	100.00
V2	alert_test	otbn_alert_test	15.000s	66.151us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	23.507us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	86.330us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	86.330us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	48.922us	5	5	100.00
		otbn_csr_rw	6.000s	17.120us	20	20	100.00
		otbn_csr_aliasing	5.000s	134.374us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	38.701us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	48.922us	5	5	100.00
		otbn_csr_rw	6.000s	17.120us	20	20	100.00
		otbn_csr_aliasing	5.000s	134.374us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	38.701us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	18.000s	78.905us	10	10	100.00
		otbn_dmem_err	12.000s	57.214us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	238.480us	5	5	100.00
		otbn_controller_ispr_rdata_err	58.000s	241.035us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	68.358us	5	5	100.00
		otbn_urnd_err	8.000s	11.836us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	139.356us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.466us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	350.604us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
		otbn_tl_intg_err	29.000s	161.103us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	235.182us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	611.247us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	57.214us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	78.905us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	161.103us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	15.000s	94.337us	52	60	86.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	78.905us	10	10	100.00
		otbn_dmem_err	12.000s	57.214us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	15.756us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	139.356us	5	5	100.00
		otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	78.905us	10	10	100.00
		otbn_dmem_err	12.000s	57.214us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	15.756us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	139.356us	5	5	100.00
		otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	15.000s	94.337us	52	60	86.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	78.905us	10	10	100.00
		otbn_dmem_err	12.000s	57.214us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	15.756us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	139.356us	5	5	100.00
		otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	58.084us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	20.084us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	58.000s	367.253us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	58.000s	367.253us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	37.000s	152.984us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	69.714us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	2.052ms	3	5	60.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	2.052ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	19.000s	42.192us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.867m	1.271ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	226.935us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.033m	501.864us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.350m	4.191ms	4	5	80.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.983m	160.827ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			569	585	97.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.60	95.35	99.69	93.43	92.66	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

2.otbn_escalate.41102146715764713150629943406560874841348745586098012383150132351431263449961
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1839577 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1839577 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1839577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_escalate.111963316027551603877343624670743236521481016302957980366940787145857224819785
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4834842 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4834842 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4834842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test otbn_stress_all has 2 failures.

1.otbn_stress_all.7880330281389166053994843734045290864349811040232821536441946023316271902634
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5702, which encodes to -2851, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

2.otbn_stress_all.16730411716172221775606308137067923704745723585527340386328856768341038180097
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5298, which encodes to -2649, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_single has 1 failures.

80.otbn_single.1596761064427322201986730561236512525826257689375773278027351973577585629894
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/80.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -6406, which encodes to -3203, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 0.otbn_stack_addr_integ_chk.32747076864150956901375698644819084948360214076667005097307125372223091414772
    Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2051867626 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x9c090018)
  UVM_INFO @ 2051867626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stack_addr_integ_chk.58916005033070820889391142839390332955241844413849614251903308425427384842819
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2044862804 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x69170018)
  UVM_INFO @ 2044862804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

8.otbn_escalate.108142277827744489558149196017703208678174911582810948955816003201879451979506
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 55409854 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  55409854 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  55409854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.otbn_escalate.52731208012263325173822653963595040462124414268095667376524458710233142276728
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 94336716 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  94336716 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  94336716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:401) [scoreboard] Check failed (pending_start_tl_trans) Saw start transaction without corresponding write to CMD has 1 failures:
- Test otbn_sec_cm has 1 failures.
  - 4.otbn_sec_cm.40995830340265121581962762644232976033355607476686632615344680078631117801658
    Line 2874, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
```
  UVM_FATAL @ 5474819838 ps: (otbn_scoreboard.sv:401) [uvm_test_top.env.scoreboard] Check failed (pending_start_tl_trans) Saw start transaction without corresponding write to CMD
  UVM_INFO @ 5474819838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.52875157852103170098378560346430167190912686893783669393426173768700157868937
    Line 521, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 851973808 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 851973808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 8.otbn_partial_wipe.5983199926473953830991049645016517876930223441844912617129165910960746838199
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6423071 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6423071 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6423071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```