3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 67.199us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 16.793us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 31.194us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 96.957us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 20.833us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 15.000s | 84.823us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 31.194us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 20.833us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 53.000s | 3.969ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 27.000s | 440.414us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 1.183m | 362.165us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.017m | 498.558us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.450m | 461.653us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.067m | 193.441us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 42.000s | 928.864us | 46 | 60 | 76.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 18.729us | 3 | 5 | 60.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 14.000s | 87.741us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 15.881us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 20.643us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 9.000s | 99.351us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 9.000s | 99.351us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 16.793us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 31.194us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 20.833us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 35.880us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 16.793us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 31.194us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 20.833us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 8.000s | 35.880us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 246 | 93.50 | |||
| V2S | mem_integrity | otbn_imem_err | 22.000s | 92.874us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.517m | 373.996us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 11.000s | 57.642us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 12.000s | 62.598us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 233.401us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 13.804us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 25.977us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 12.931us | 1 | 2 | 50.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 9.000s | 29.292us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 44.000s | 271.208us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 31.000s | 165.397us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 67.199us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 1.517m | 373.996us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 22.000s | 92.874us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 44.000s | 271.208us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 42.000s | 928.864us | 46 | 60 | 76.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 22.000s | 92.874us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.517m | 373.996us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.729us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 8.000s | 25.977us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 22.000s | 92.874us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.517m | 373.996us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.729us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 8.000s | 25.977us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 42.000s | 928.864us | 46 | 60 | 76.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 22.000s | 92.874us | 10 | 10 | 100.00 |
| otbn_dmem_err | 1.517m | 373.996us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 18.729us | 3 | 5 | 60.00 | ||
| otbn_illegal_mem_acc | 8.000s | 25.977us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 12.000s | 43.138us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 11.000s | 27.960us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.633m | 1.209ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.633m | 1.209ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 21.667us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 12.000s | 65.697us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 55.000s | 2.005ms | 2 | 5 | 40.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 55.000s | 2.005ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 26.000s | 126.840us | 6 | 7 | 85.71 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.450m | 461.653us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 10.000s | 19.806us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.717m | 475.824us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 8.267m | 3.114ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 157 | 163 | 96.32 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 33.400m | 127.133ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 561 | 585 | 95.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 11 | 11 | 9 | 81.82 |
| V2S | 20 | 20 | 16 | 80.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.89 | 99.60 | 95.40 | 99.69 | 93.58 | 92.62 | 97.44 | 91.38 | 98.74 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:
Test otbn_zero_state_err_urnd has 2 failures.
0.otbn_zero_state_err_urnd.87898861853776804355114790425537934894290355429924098784580612847447119590481
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12988913 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 12988913 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 12988913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_zero_state_err_urnd.41331927843407017306992994298770330858377111241685123582770308839192836106321
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18728593 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 18728593 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 18728593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 4 failures.
13.otbn_escalate.90667405387205136243862637049318848823945325639183825834311832452500581281424
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 325085191 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 325085191 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 325085191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.otbn_escalate.89020645409312711632595759834918289273431788493071807996237433809218720480351
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21305780 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 21305780 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 21305780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:
5.otbn_escalate.113452508039933740240205307943089631581190107256786734302196799721632057390808
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 10341880 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 10341880 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 10341880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.otbn_escalate.45445806913916034560884476003427326408385263604467816269444026120023795875987
Line 304, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8239076 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 8239076 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 8239076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 5 failures:
6.otbn_escalate.107028265820167276871569192617006485219006822742566593396100846241107043694052
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 53155415 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 53155415 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 53155415 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 53155415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.otbn_escalate.56114439421861854730155212224324244687302499998882875276925931088140960935049
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4560210 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 4560210 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 4560210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 3 failures:
0.otbn_stack_addr_integ_chk.27191711210112492162528162331403602350632500571587403732269874890465576133506
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 2013747107 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xbe540018)
UVM_INFO @ 2013747107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_stack_addr_integ_chk.61700938022109909371438000989593621926063236814441371693687919193472013153651
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 2017769761 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x2f420018)
UVM_INFO @ 2017769761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
Test otbn_mem_gnt_acc_err has 1 failures.
0.otbn_mem_gnt_acc_err.79687858204258180622940607923108137219369805918554721469574963469576519064198
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6838, which encodes to -3419, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_stress_all_with_rand_reset has 1 failures.
1.otbn_stress_all_with_rand_reset.65775322753549573336977771670635549633894999906307951298384665866501508478493
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6098, which encodes to -3049, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
0.otbn_sec_wipe_err.110091958828766463250573751362184664900529242847354397171829845811430733803770
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 43024886 PS) Assertion tb.dut.NotBusyAndDone_A has failed
UVM_ERROR @ 43024886 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
UVM_INFO @ 43024886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
4.otbn_stress_all_with_rand_reset.91030963449280738270119169356036638845501566136004680939973101042360528220939
Line 592, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18525071106 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 18525071106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:198) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
6.otbn_partial_wipe.25790401769215724134575365712757205105940712743839851349346527947958402201408
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
UVM_FATAL @ 10468472 ps: (otbn_scoreboard.sv:198) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
UVM_INFO @ 10468472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---