OTBN Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	19.000s	64.258us	1	1	100.00
V1	single_binary	otbn_single	1.750m	423.380us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	23.378us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	50.782us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	87.732us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	16.520us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	70.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	50.782us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.520us	5	5	100.00
V1	mem_walk	otbn_mem_walk	44.000s	349.273us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	460.336us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.617m	359.307us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	1.352ms	1	1	100.00
V2	back_to_back	otbn_multi	3.167m	742.547us	10	10	100.00
V2	stress_all	otbn_stress_all	2.317m	472.451us	10	10	100.00
V2	lc_escalation	otbn_escalate	31.000s	130.469us	44	60	73.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	51.621us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	227.838us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	27.406us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	20.899us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	277.228us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	277.228us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	23.378us	5	5	100.00
		otbn_csr_rw	5.000s	50.782us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.520us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	35.282us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	23.378us	5	5	100.00
		otbn_csr_rw	5.000s	50.782us	20	20	100.00
		otbn_csr_aliasing	6.000s	16.520us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	35.282us	20	20	100.00
V2		TOTAL			230	246	93.50
V2S	mem_integrity	otbn_imem_err	19.000s	419.949us	10	10	100.00
		otbn_dmem_err	12.000s	66.015us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	106.824us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	92.307us	5	5	100.00
		otbn_mac_bignum_acc_err	43.000s	672.797us	5	5	100.00
		otbn_urnd_err	11.000s	15.718us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	64.501us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	12.485us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	203.167us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
		otbn_tl_intg_err	46.000s	336.517us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	217.258us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	19.000s	64.258us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	66.015us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	19.000s	419.949us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	46.000s	336.517us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	31.000s	130.469us	44	60	73.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	19.000s	419.949us	10	10	100.00
		otbn_dmem_err	12.000s	66.015us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	51.621us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	64.501us	5	5	100.00
		otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	19.000s	419.949us	10	10	100.00
		otbn_dmem_err	12.000s	66.015us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	51.621us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	64.501us	5	5	100.00
		otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	31.000s	130.469us	44	60	73.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	19.000s	419.949us	10	10	100.00
		otbn_dmem_err	12.000s	66.015us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	51.621us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	64.501us	5	5	100.00
		otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	45.520us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	27.610us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.150m	615.138us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.150m	615.138us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	167.214us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	92.683us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	20.977us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	20.977us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	21.000s	159.633us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.167m	742.547us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	34.050us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.750m	423.380us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.883m	3.810ms	5	5	100.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	21.300m	40.573ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			567	585	96.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.61	95.53	99.69	93.61	92.49	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

2.otbn_escalate.108451107499411702115558263004667602492585893738561529944319656790564407902343
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 9492936 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9492936 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9492936 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   9492936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.otbn_escalate.45069242984611328163106842718227590899339430835106811115892041286196744100600
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 27579077 PS) Assertion tb.MatchingStatus_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27579077 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  27579077 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  27579077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 7 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.105348257417556068028354323561544662982241705916043944341657908617848174166278
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 54123455 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  54123455 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  54123455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 6 failures.

10.otbn_escalate.29502256787567085429372126695818437560909296821151073670863245962775426481853
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 180705682 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 180705682 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 180705682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.otbn_escalate.25388245239894874322714093920215877814977069425721885693390454474961731782457
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50876710 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  50876710 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  50876710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 4.otbn_sec_wipe_err.7062066057230677751683979906416137595183970021800975218661950623108191378267
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15585777 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15585777 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15585777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 18.otbn_escalate.99334850484388402042147071969463783049584668452408478664695781242697845617783
    Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 26729428 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  26729428 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  26729428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:501) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 32.otbn_escalate.111375887769516628114794693924779077351471696299195248049862208375892015131094
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log
```
  UVM_FATAL @ 144005280 ps: (otbn_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @ 144005280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```