OTBN Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	37.231us	1	1	100.00
V1	single_binary	otbn_single	3.400m	915.313us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	24.858us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	37.777us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	357.929us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	24.034us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	69.344us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	37.777us	20	20	100.00
		otbn_csr_aliasing	6.000s	24.034us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.167m	12.764ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	352.217us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	36.000s	218.754us	10	10	100.00
V2	multi_error	otbn_multi_err	58.000s	152.907us	1	1	100.00
V2	back_to_back	otbn_multi	4.317m	5.064ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.833m	277.835us	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	42.476us	49	60	81.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	37.063us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	43.106us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	53.113us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	19.400us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	574.675us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	574.675us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	24.858us	5	5	100.00
		otbn_csr_rw	6.000s	37.777us	20	20	100.00
		otbn_csr_aliasing	6.000s	24.034us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	56.514us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	24.858us	5	5	100.00
		otbn_csr_rw	6.000s	37.777us	20	20	100.00
		otbn_csr_aliasing	6.000s	24.034us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	56.514us	20	20	100.00
V2		TOTAL			235	246	95.53
V2S	mem_integrity	otbn_imem_err	11.000s	33.710us	10	10	100.00
		otbn_dmem_err	14.000s	21.806us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	22.000s	187.950us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	58.423us	5	5	100.00
		otbn_mac_bignum_acc_err	26.000s	825.314us	5	5	100.00
		otbn_urnd_err	8.000s	114.845us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	13.000s	54.348us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	95.414us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	26.950us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
		otbn_tl_intg_err	1.000m	414.041us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	171.348us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	37.231us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	21.806us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	33.710us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.000m	414.041us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	42.476us	49	60	81.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	33.710us	10	10	100.00
		otbn_dmem_err	14.000s	21.806us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	37.063us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	54.348us	5	5	100.00
		otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	33.710us	10	10	100.00
		otbn_dmem_err	14.000s	21.806us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	37.063us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	54.348us	5	5	100.00
		otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	42.476us	49	60	81.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	33.710us	10	10	100.00
		otbn_dmem_err	14.000s	21.806us	15	15	100.00
		otbn_zero_state_err_urnd	7.000s	37.063us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	54.348us	5	5	100.00
		otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	44.062us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	59.785us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	32.000s	950.891us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	32.000s	950.891us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	37.421us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	60.547us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.200m	2.005ms	2	5	40.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.200m	2.005ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	64.847us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.317m	5.064ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	46.955us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.400m	915.313us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.283m	3.837ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.450m	2.326ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			566	585	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.61	95.48	99.69	93.40	92.87	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

3.otbn_stack_addr_integ_chk.55023523808817164888594514911291400858186986609565089261017477141839326414918
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 147387877 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 147387877 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 147387877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 4 failures.

8.otbn_escalate.86101671673974586156142968343188544938125258480089809739938528681853194049908
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 135280906 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 135280906 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 135280906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.85687196859248505287193625304681417684997879580859458913050254617052139472803
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42475998 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  42475998 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  42475998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:

Test otbn_escalate has 5 failures.

18.otbn_escalate.58394477364942715916856258721065148211115350916975768905761077774910710153773
Line 307, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 31357293 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  31357293 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  31357293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.otbn_escalate.47904995558948301775562118524172305841142557558246719541179504346871965782445
Line 308, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 89646182 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  89646182 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  89646182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 2 failures:

Test otbn_escalate has 2 failures.

1.otbn_escalate.41291030005389523207984234507191823082762139255386435944536478626195747010683
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 2266074 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   2266074 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   2266074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.otbn_escalate.6680200122389356297115501962929765364964762404982834729630709777621210411209
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 4613729 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4613729 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4613729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 2 failures:
- Test otbn_stack_addr_integ_chk has 2 failures.
  - 1.otbn_stack_addr_integ_chk.97627850449554437573523948256217815007238903560960343803070611164533498418860
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2005077889 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xddf10018)
  UVM_INFO @ 2005077889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stack_addr_integ_chk.15292294560352370277075666855118196854062037847482287571874772983953580222647
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 2028265748 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x5b3e0018)
  UVM_INFO @ 2028265748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 3.otbn_stress_all_with_rand_reset.114482346720285553714267306176887774386607041837978798551725964975860315344348
    Line 1020, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2326163725 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2326163725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otbn_stress_all_with_rand_reset.16712347230113742883517211880271431463228593177321130314534847493882602337320
    Line 369, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 210762027 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 210762027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.75945110409281675059362067265789417992848243171024270707995530380600885424597
    Line 665, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1256507144 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1256507144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.94392672363727508278041360637989551302493729058704574951824794417598968396666
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14302370 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14302370 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14302370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otbn_single has 1 failures.

28.otbn_single.3277609619726978382738674825201224822787660000736684919904446728472995672468
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/28.otbn_single/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -5542, which encodes to -2771, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1