OTBN Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	37.154us	1	1	100.00
V1	single_binary	otbn_single	2.183m	1.122ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	52.715us	5	5	100.00
V1	csr_rw	otbn_csr_rw	5.000s	11.301us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	542.122us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	22.694us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	63.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	11.301us	20	20	100.00
		otbn_csr_aliasing	5.000s	22.694us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	1.237ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	854.990us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	41.000s	193.102us	10	10	100.00
V2	multi_error	otbn_multi_err	1.300m	372.326us	1	1	100.00
V2	back_to_back	otbn_multi	1.333m	959.418us	10	10	100.00
V2	stress_all	otbn_stress_all	2.400m	970.375us	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	302.335us	52	60	86.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	67.455us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	151.365us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	18.943us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	14.391us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	131.909us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	131.909us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	52.715us	5	5	100.00
		otbn_csr_rw	5.000s	11.301us	20	20	100.00
		otbn_csr_aliasing	5.000s	22.694us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	39.079us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	52.715us	5	5	100.00
		otbn_csr_rw	5.000s	11.301us	20	20	100.00
		otbn_csr_aliasing	5.000s	22.694us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	39.079us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	13.000s	42.186us	10	10	100.00
		otbn_dmem_err	14.000s	49.172us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	220.900us	5	5	100.00
		otbn_controller_ispr_rdata_err	21.000s	71.906us	5	5	100.00
		otbn_mac_bignum_acc_err	10.000s	32.690us	5	5	100.00
		otbn_urnd_err	6.000s	9.764us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	29.123us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	29.301us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	26.640us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
		otbn_tl_intg_err	29.000s	195.994us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.117m	463.423us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	37.154us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	49.172us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	42.186us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	195.994us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	302.335us	52	60	86.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	42.186us	10	10	100.00
		otbn_dmem_err	14.000s	49.172us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.455us	3	5	60.00
		otbn_illegal_mem_acc	7.000s	29.123us	5	5	100.00
		otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	42.186us	10	10	100.00
		otbn_dmem_err	14.000s	49.172us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.455us	3	5	60.00
		otbn_illegal_mem_acc	7.000s	29.123us	5	5	100.00
		otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	302.335us	52	60	86.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	42.186us	10	10	100.00
		otbn_dmem_err	14.000s	49.172us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	67.455us	3	5	60.00
		otbn_illegal_mem_acc	7.000s	29.123us	5	5	100.00
		otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	54.069us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	61.214us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	47.000s	468.964us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	47.000s	468.964us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	34.030us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	74.416us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	33.106us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	33.106us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	94.904us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.333m	959.418us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	18.000s	45.044us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.183m	1.122ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.267m	4.450ms	5	5	100.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	16.533m	3.633ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.62	95.57	99.70	93.55	92.47	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 4 failures:

Test otbn_escalate has 4 failures.

5.otbn_escalate.97772363995331827035452766657650231302691352488617635985587160448401136949654
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 1826807 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1826807 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1826807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.102960184684399833675815910786733832500355685019204396942093166990831939631775
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 2310839 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   2310839 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   2310839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

1.otbn_zero_state_err_urnd.56718190526807765077116236582700082427183096882897672040745806874590565907905
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19552661 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19552661 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19552661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

8.otbn_escalate.32884497792212647607630431826775138973609733932030657409139390424220767069893
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12808316 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12808316 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12808316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.82289786595806834519446962862738428871370524915115651197224148404745861397067
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 67735943 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  67735943 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  67735943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test otbn_zero_state_err_urnd has 1 failures.

2.otbn_zero_state_err_urnd.15552126453120570439713558901586055803281763994650563788795193516861299072007
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4330, which encodes to -2165, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Test otbn_stress_all_with_rand_reset has 1 failures.

7.otbn_stress_all_with_rand_reset.42375532064030360643229807570215915276783291394911236449063733245389439139753
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log

      gen_res = self.gen(model, program, end)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
      gen_res = generator.gen(self.gens, model, program)
    File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
      off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
    File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
      '' if self.signed else 'un', doc_lo, doc_hi))
  ValueError: Cannot encode the value -4718, which encodes to -2359, as a 12-bit signed value. Possible range: -4096..4094.
  ninja: build stopped: subcommand failed.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

10.otbn_escalate.5129468138265461982943106563313006148974646306329395119341060682257776742613
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 9209974 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   9209974 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   9209974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.68802718835152401417688452271899863261462293430991175799626000228230102638367
Line 304, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 31717387 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  31717387 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  31717387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:198) [scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register. has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 1.otbn_partial_wipe.84850646530823035025586195463418094810630179528809047242335556453829759721280
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log
```
  UVM_FATAL @   7063279 ps: (otbn_scoreboard.sv:198) [uvm_test_top.env.scoreboard] Check failed (!cfg.clk_rst_vif.rst_n || !pending_start_tl_trans) Model ignored a write to the CMD register.
  UVM_INFO @   7063279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 3.otbn_sec_wipe_err.55706518479752846633152680968380198794269653620528798849225033414818125417726
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 16918521 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  16918521 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  16918521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```