OTBN Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	197.032us	1	1	100.00
V1	single_binary	otbn_single	58.000s	811.083us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	22.476us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	41.176us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	380.993us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	13.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	42.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	41.176us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.169us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	7.138ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	369.953us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.033m	241.679us	10	10	100.00
V2	multi_error	otbn_multi_err	57.000s	309.158us	1	1	100.00
V2	back_to_back	otbn_multi	1.433m	1.416ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.317m	535.443us	10	10	100.00
V2	lc_escalation	otbn_escalate	40.000s	144.067us	47	60	78.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	34.876us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	25.000s	241.356us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	26.051us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	26.400us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	398.565us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	398.565us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	22.476us	5	5	100.00
		otbn_csr_rw	6.000s	41.176us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.169us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.149us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	22.476us	5	5	100.00
		otbn_csr_rw	6.000s	41.176us	20	20	100.00
		otbn_csr_aliasing	5.000s	13.169us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	24.149us	20	20	100.00
V2		TOTAL			233	246	94.72
V2S	mem_integrity	otbn_imem_err	15.000s	58.513us	10	10	100.00
		otbn_dmem_err	20.000s	233.153us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	33.000s	173.178us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	61.843us	5	5	100.00
		otbn_mac_bignum_acc_err	31.000s	104.732us	5	5	100.00
		otbn_urnd_err	8.000s	26.019us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	21.215us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	77.620us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	25.470us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
		otbn_tl_intg_err	31.000s	203.232us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	237.070us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	197.032us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	20.000s	233.153us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	58.513us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	203.232us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	40.000s	144.067us	47	60	78.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	58.513us	10	10	100.00
		otbn_dmem_err	20.000s	233.153us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	34.876us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.215us	5	5	100.00
		otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	58.513us	10	10	100.00
		otbn_dmem_err	20.000s	233.153us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	34.876us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.215us	5	5	100.00
		otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	40.000s	144.067us	47	60	78.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	58.513us	10	10	100.00
		otbn_dmem_err	20.000s	233.153us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	34.876us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	21.215us	5	5	100.00
		otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	35.842us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	19.536us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	41.000s	127.496us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	41.000s	127.496us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	28.123us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	280.867us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	46.505us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	46.505us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	59.271us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.433m	1.416ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	23.000s	64.587us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	58.000s	811.083us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.133m	7.248ms	5	5	100.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	14.333m	3.641ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	99.61	95.44	99.69	93.41	92.98	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

5.otbn_escalate.44951532580953732218224187006791239101347270218848143858799385417051345263244
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 1494313 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1494313 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1494313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.otbn_escalate.88693989070851150433827395493838766162415475032854873092398701668401910117438
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 2120817 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   2120817 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   2120817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 5 failures:

Test otbn_escalate has 5 failures.

1.otbn_escalate.11093004974175251459534821903049160216600049412100144256621444122781686728180
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 15098136 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  15098136 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  15098136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_escalate.48879274838530052327142201859435319287341904366003812592150990102680601193820
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5502896 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5502896 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5502896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.5338843168093160954214010363218723966329265386930453862953358993522920572233
    Line 646, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1384885166 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1384885166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 1.otbn_partial_wipe.4912785273384218909880096420836132440794766617090097712775475099862789489223
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6847953 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6847953 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6847953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```