OTBN Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	142.948us	1	1	100.00
V1	single_binary	otbn_single	48.000s	196.819us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	21.601us	5	5	100.00
V1	csr_rw	otbn_csr_rw	15.000s	46.377us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	15.000s	270.475us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	15.000s	11.450us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	16.000s	293.191us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	15.000s	46.377us	20	20	100.00
		otbn_csr_aliasing	15.000s	11.450us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	4.803ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	28.000s	367.671us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	57.000s	248.558us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	822.052us	1	1	100.00
V2	back_to_back	otbn_multi	8.783m	2.288ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.317m	916.767us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	1.047ms	44	60	73.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	31.414us	3	5	60.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.817m	439.130us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	26.547us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	17.843us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	439.039us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	439.039us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	21.601us	5	5	100.00
		otbn_csr_rw	15.000s	46.377us	20	20	100.00
		otbn_csr_aliasing	15.000s	11.450us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	141.802us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	21.601us	5	5	100.00
		otbn_csr_rw	15.000s	46.377us	20	20	100.00
		otbn_csr_aliasing	15.000s	11.450us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	141.802us	20	20	100.00
V2		TOTAL			228	246	92.68
V2S	mem_integrity	otbn_imem_err	12.000s	36.867us	10	10	100.00
		otbn_dmem_err	16.000s	156.609us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	71.734us	5	5	100.00
		otbn_controller_ispr_rdata_err	43.000s	157.220us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	66.191us	5	5	100.00
		otbn_urnd_err	12.000s	18.649us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	42.530us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	22.461us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	28.734us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
		otbn_tl_intg_err	29.000s	181.075us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	221.751us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	142.948us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	156.609us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	36.867us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	181.075us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	1.047ms	44	60	73.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	36.867us	10	10	100.00
		otbn_dmem_err	16.000s	156.609us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.414us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	42.530us	5	5	100.00
		otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.867us	10	10	100.00
		otbn_dmem_err	16.000s	156.609us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.414us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	42.530us	5	5	100.00
		otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	1.047ms	44	60	73.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	36.867us	10	10	100.00
		otbn_dmem_err	16.000s	156.609us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.414us	3	5	60.00
		otbn_illegal_mem_acc	9.000s	42.530us	5	5	100.00
		otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	59.360us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	12.739us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.683m	443.346us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.683m	443.346us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	274.781us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	70.575us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	140.518us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	140.518us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	103.239us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	8.783m	2.288ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	46.119us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	48.000s	196.819us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.117m	12.073ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	13.483m	56.498ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			564	585	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.61	95.53	99.70	93.49	92.76	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 8 failures:

Test otbn_escalate has 8 failures.

2.otbn_escalate.43545153345199107527091427356521227838623835752419921468473985672101664428504
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 3726727 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3726727 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3726727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_escalate.36038474937283275269450616441989836035003001515919474977920186425995134510578
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 3384742 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3384742 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3384742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_zero_state_err_urnd has 2 failures.

2.otbn_zero_state_err_urnd.113353930787867272126648630897929553918431532178627277289977640061873524516423
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25951920 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  25951920 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  25951920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_zero_state_err_urnd.109254302056078518759667755375219675818457940922420950015607804438804378110568
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29488521 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  29488521 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29488521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 3 failures.

22.otbn_escalate.15842839559899194569077902950007560836123389845949744017365231038511664078798
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 99564984 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  99564984 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  99564984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.otbn_escalate.23604961097997070878775326791345343922386286640233812988041998242855122007663
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43872347 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  43872347 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  43872347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:

Test otbn_escalate has 4 failures.

3.otbn_escalate.20655762165132902497046866294499272519162665613613356016398721666982042916326
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5485978 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   5485978 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   5485978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.27958322353164975584926033223021389999405692948501798460782391922377808935556
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 11048004 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  11048004 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  11048004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 4.otbn_rf_base_intg_err.61080121747632385944048104253786939609267070354258683795533984469149165428852
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @  15313348 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  15313348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 4.otbn_sec_wipe_err.99315095359120855608794070478363283337564027192069369638487908751456214481654
    Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 16531213 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  16531213 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  16531213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 9.otbn_rf_base_intg_err.74286698126592913180700483889906076821490310573494730600290341892091128493684
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  31265669 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  31265669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 37.otbn_escalate.30984293200764397526646844509107446485161129016976883980560418455843582840172
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/37.otbn_escalate/latest/run.log
```
  UVM_FATAL @  37831560 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @  37831560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```