OTBN Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	9.000s	61.169us	1	1	100.00
V1	single_binary	otbn_single	34.000s	93.554us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	20.175us	5	5	100.00
V1	csr_rw	otbn_csr_rw	20.000s	17.188us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	36.705us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	25.027us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	97.750us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	20.000s	17.188us	20	20	100.00
		otbn_csr_aliasing	9.000s	25.027us	5	5	100.00
V1	mem_walk	otbn_mem_walk	54.000s	19.889ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	357.023us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	46.000s	507.689us	10	10	100.00
V2	multi_error	otbn_multi_err	1.150m	148.498us	1	1	100.00
V2	back_to_back	otbn_multi	7.217m	1.917ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.400m	721.113us	10	10	100.00
V2	lc_escalation	otbn_escalate	25.000s	162.202us	54	60	90.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	47.448us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	22.000s	59.930us	10	10	100.00
V2	alert_test	otbn_alert_test	15.000s	51.615us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	12.331us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	154.686us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	154.686us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	20.175us	5	5	100.00
		otbn_csr_rw	20.000s	17.188us	20	20	100.00
		otbn_csr_aliasing	9.000s	25.027us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	39.412us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	20.175us	5	5	100.00
		otbn_csr_rw	20.000s	17.188us	20	20	100.00
		otbn_csr_aliasing	9.000s	25.027us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	39.412us	20	20	100.00
V2		TOTAL			240	246	97.56
V2S	mem_integrity	otbn_imem_err	16.000s	57.263us	10	10	100.00
		otbn_dmem_err	18.000s	73.548us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	58.394us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	391.782us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	107.158us	5	5	100.00
		otbn_urnd_err	12.000s	54.794us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	27.773us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	6.000s	154.718us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	87.318us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
		otbn_tl_intg_err	55.000s	405.072us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	34.000s	225.837us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	9.000s	61.169us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	73.548us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	57.263us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	55.000s	405.072us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	162.202us	54	60	90.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	57.263us	10	10	100.00
		otbn_dmem_err	18.000s	73.548us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.448us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	27.773us	5	5	100.00
		otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	57.263us	10	10	100.00
		otbn_dmem_err	18.000s	73.548us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.448us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	27.773us	5	5	100.00
		otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	162.202us	54	60	90.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	57.263us	10	10	100.00
		otbn_dmem_err	18.000s	73.548us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	47.448us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	27.773us	5	5	100.00
		otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	64.789us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	20.962us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	48.000s	531.513us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	48.000s	531.513us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	20.407us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	23.000s	710.537us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	89.483us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	89.483us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	102.544us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	7.217m	1.917ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	64.922us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	34.000s	93.554us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.617m	4.282ms	5	5	100.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.217m	2.248ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			575	585	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.62	95.58	99.71	93.52	92.51	100.00	98.83	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

18.otbn_escalate.84940171812472962194363844044507933432078441862944023946131686639276435147684
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 3603102 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3603102 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3603102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.otbn_escalate.87425447303523640543758541283735456182081671232138145870819567181420126990517
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 1069992 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   1069992 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   1069992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_ctrl_redun has 1 failures.

6.otbn_ctrl_redun.108378232141863034121492165703694655589598865470270445833108165532482151371464
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20183123 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 20183123 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  20183123 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  20183123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

17.otbn_escalate.5741702550081109916217294143486100780040245850719960215481986343129261420712
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17774077 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17774077 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17774077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 2 failures:

Test otbn_escalate has 2 failures.

20.otbn_escalate.115072205430420919221709048609748199535557804960253696358863833429558720884905
Line 303, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 19448701 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  19448701 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  19448701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.otbn_escalate.33873199038005727543616914593940697712488838332457201335860056031960721134044
Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 26633407 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  26633407 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  26633407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.72077348484797459442471495243924128406779132742091375428909905406918626947220
    Line 480, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1426316826 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1426316826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.34906584189002964657081189166701058011801393658384016116490432945956812501767
    Line 327, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  71240614 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  71240614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.61577947384689578298654173828227636727252933956033922211484597040360728281744
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3375743 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3375743 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3375743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```