OTBN Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	139.803us	1	1	100.00
V1	single_binary	otbn_single	1.517m	642.785us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	22.004us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	33.382us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	142.582us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	15.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	50.753us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	33.382us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.939us	5	5	100.00
V1	mem_walk	otbn_mem_walk	33.000s	1.159ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	1.649ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	55.000s	1.150ms	10	10	100.00
V2	multi_error	otbn_multi_err	1.133m	299.125us	1	1	100.00
V2	back_to_back	otbn_multi	1.900m	1.876ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.683m	1.251ms	10	10	100.00
V2	lc_escalation	otbn_escalate	29.000s	79.727us	50	60	83.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	225.726us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	238.190us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	26.443us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	25.773us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	408.778us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	408.778us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	22.004us	5	5	100.00
		otbn_csr_rw	7.000s	33.382us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.939us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	36.500us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	22.004us	5	5	100.00
		otbn_csr_rw	7.000s	33.382us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.939us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	36.500us	20	20	100.00
V2		TOTAL			236	246	95.93
V2S	mem_integrity	otbn_imem_err	15.000s	40.971us	10	10	100.00
		otbn_dmem_err	11.000s	80.819us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	112.639us	5	5	100.00
		otbn_controller_ispr_rdata_err	46.000s	189.942us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	123.513us	5	5	100.00
		otbn_urnd_err	8.000s	51.782us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	22.276us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	16.646us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	80.754us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
		otbn_tl_intg_err	31.000s	197.826us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	29.000s	481.090us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	139.803us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	80.819us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	40.971us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	197.826us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	29.000s	79.727us	50	60	83.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	40.971us	10	10	100.00
		otbn_dmem_err	11.000s	80.819us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	225.726us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	22.276us	5	5	100.00
		otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	40.971us	10	10	100.00
		otbn_dmem_err	11.000s	80.819us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	225.726us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	22.276us	5	5	100.00
		otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	29.000s	79.727us	50	60	83.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	40.971us	10	10	100.00
		otbn_dmem_err	11.000s	80.819us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	225.726us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	22.276us	5	5	100.00
		otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	53.044us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	66.357us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.183m	662.267us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.183m	662.267us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	28.393us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	20.000s	123.723us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	105.093us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	105.093us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	39.396us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.900m	1.876ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	26.000s	145.717us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.517m	642.785us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	14.133m	4.262ms	5	5	100.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	30.517m	38.173ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			574	585	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.61	95.49	99.70	93.67	92.49	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 6 failures:

Test otbn_escalate has 6 failures.

18.otbn_escalate.48184987597181408024812743981126257006838474048040932470393668033932415560356
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 4777726 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   4777726 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   4777726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.otbn_escalate.111335544571605053444842409105011401311326940709436706114249583350673978476295
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 50967806 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  50967806 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  50967806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

0.otbn_escalate.109411975736316761807542075821494738706571539965674716189532991282895178615666
Line 310, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 57337328 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  57337328 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  57337328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.45407159312559505838106967875951618336612345883009663328492806921980754468610
Line 304, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 11812182 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  11812182 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  11812182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 4.otbn_stack_addr_integ_chk.93925584885441901002699561299430956280134656432790449979551198035649441389220
    Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38995818 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38995818 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  38995818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): (time * NS) Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 23.otbn_escalate.87409050570172830130274004230906358681272222697802727748319256737436180430500
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/23.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 8692 NS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   8692000 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   8692000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```