OTBN Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	72.007us	1	1	100.00
V1	single_binary	otbn_single	3.300m	1.007ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	19.812us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	15.084us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	177.581us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	23.130us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	22.219us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	15.084us	20	20	100.00
		otbn_csr_aliasing	6.000s	23.130us	5	5	100.00
V1	mem_walk	otbn_mem_walk	44.000s	1.830ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	129.312us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.467m	365.799us	10	10	100.00
V2	multi_error	otbn_multi_err	1.067m	143.103us	1	1	100.00
V2	back_to_back	otbn_multi	8.133m	2.387ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.417m	348.358us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.650m	340.632us	53	60	88.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	48.417us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	54.000s	191.552us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	47.228us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	13.405us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	73.808us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	73.808us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	19.812us	5	5	100.00
		otbn_csr_rw	10.000s	15.084us	20	20	100.00
		otbn_csr_aliasing	6.000s	23.130us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	29.613us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	19.812us	5	5	100.00
		otbn_csr_rw	10.000s	15.084us	20	20	100.00
		otbn_csr_aliasing	6.000s	23.130us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	29.613us	20	20	100.00
V2		TOTAL			239	246	97.15
V2S	mem_integrity	otbn_imem_err	30.000s	126.600us	10	10	100.00
		otbn_dmem_err	15.000s	47.065us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	214.726us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	22.476us	5	5	100.00
		otbn_mac_bignum_acc_err	18.000s	67.129us	5	5	100.00
		otbn_urnd_err	10.000s	19.327us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	25.576us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	24.230us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	62.887us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
		otbn_tl_intg_err	44.000s	288.345us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	228.297us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	72.007us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	47.065us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	30.000s	126.600us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	44.000s	288.345us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.650m	340.632us	53	60	88.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	30.000s	126.600us	10	10	100.00
		otbn_dmem_err	15.000s	47.065us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.417us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.576us	5	5	100.00
		otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	30.000s	126.600us	10	10	100.00
		otbn_dmem_err	15.000s	47.065us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.417us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.576us	5	5	100.00
		otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.650m	340.632us	53	60	88.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	30.000s	126.600us	10	10	100.00
		otbn_dmem_err	15.000s	47.065us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	48.417us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	25.576us	5	5	100.00
		otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	28.313us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	31.094us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	3.833m	1.069ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	3.833m	1.069ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	29.000s	106.843us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	303.597us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	53.617us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	53.617us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	34.000s	132.081us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	8.133m	2.387ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	85.089us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.300m	1.007ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	23.317m	8.317ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.217m	7.617ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			573	585	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.99	99.62	95.67	99.71	93.55	92.96	100.00	98.83	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 8 failures:

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.87545261986820092076182878688353562163801098904158516858986493901307779631475
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 132081064 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 132081064 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 132081064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 7 failures.

12.otbn_escalate.18933760485380309408709742352777149379320315498996368795477567249614194395039
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43768474 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  43768474 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  43768474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.otbn_escalate.73286737529421748757010469690811331855378989126013855500795885642951150479824
Line 297, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15530358 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15530358 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15530358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.50191673834380378586943905801692890355748476694029491937354288164642931725875
    Line 343, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 146618433 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 146618433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:826) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.78629805284873698120617173819216960569999021995069581529415760178969604588967
    Line 365, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 675952372 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 675952372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 9.otbn_rf_base_intg_err.23098205968252270256392914708135618418613815175196313933297702067230070546819
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 2030224160 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x334b0018)
  UVM_INFO @ 2030224160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 9.otbn_partial_wipe.47216297278585918053126981600618837146773025390422865533280821870560888042452
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 8744320 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   8744320 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   8744320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```